@@ -500,19 +500,11 @@ unsigned configure_IEEE_phy_speed( XEmacPs * xemacpsp,
500500 return 0 ;
501501}
502502
503- static void SetUpSLCRDivisors ( int mac_baseaddr ,
504- int speed )
503+ static void WriteSLCRDivisors (int mac_baseaddr ,
504+ u32 SlcrDiv0 ,
505+ u32 SlcrDiv1 )
505506{
506507 volatile u32 slcrBaseAddress ;
507-
508- #ifndef PEEP
509- u32 SlcrDiv0 = 0 ;
510- u32 SlcrDiv1 = 0 ;
511- u32 SlcrTxClkCntrl ;
512- #endif
513-
514- * ( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE ;
515-
516508 if ( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
517509 {
518510 slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR ;
@@ -521,8 +513,28 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
521513 {
522514 slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR ;
523515 }
516+ u32 SlcrTxClkCntrl = * ( volatile unsigned int * ) ( slcrBaseAddress );
517+ SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK ;
518+ SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
519+ SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
520+ * ( volatile unsigned int * ) ( slcrBaseAddress ) = SlcrTxClkCntrl ;
521+ }
522+
523+ static void SetUpSLCRDivisors ( int mac_baseaddr ,
524+ int speed )
525+ {
526+ * ( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE ;
524527
525528 #ifdef PEEP
529+ volatile u32 slcrBaseAddress ;
530+ if ( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
531+ {
532+ slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR ;
533+ }
534+ else
535+ {
536+ slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR ;
537+ }
526538 if ( speed == 1000 )
527539 {
528540 * ( volatile unsigned int * ) ( slcrBaseAddress ) =
@@ -544,15 +556,17 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
544556 if ( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
545557 {
546558 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
547- SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 ;
548- SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 ;
559+ u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 ;
560+ u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 ;
561+ WriteSLCRDivisors (mac_baseaddr , SlcrDiv0 , SlcrDiv1 );
549562 #endif
550563 }
551564 else
552565 {
553566 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
554- SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 ;
555- SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 ;
567+ u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 ;
568+ u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 ;
569+ WriteSLCRDivisors (mac_baseaddr , SlcrDiv0 , SlcrDiv1 );
556570 #endif
557571 }
558572 }
@@ -561,15 +575,17 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
561575 if ( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
562576 {
563577 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
564- SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 ;
565- SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 ;
578+ u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 ;
579+ u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 ;
580+ WriteSLCRDivisors (mac_baseaddr , SlcrDiv0 , SlcrDiv1 );
566581 #endif
567582 }
568583 else
569584 {
570585 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
571- SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 ;
572- SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 ;
586+ u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 ;
587+ u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 ;
588+ WriteSLCRDivisors (mac_baseaddr , SlcrDiv0 , SlcrDiv1 );
573589 #endif
574590 }
575591 }
@@ -578,37 +594,24 @@ static void SetUpSLCRDivisors( int mac_baseaddr,
578594 if ( ( unsigned long ) mac_baseaddr == EMAC0_BASE_ADDRESS )
579595 {
580596 #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
581- SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 ;
582- SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 ;
597+ u32 SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 ;
598+ u32 SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 ;
599+ WriteSLCRDivisors (mac_baseaddr , SlcrDiv0 , SlcrDiv1 );
583600 #endif
584601 }
585602 else
586603 {
587604 #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
588- SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 ;
589- SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 ;
605+ u32 SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 ;
606+ u32 SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 ;
607+ WriteSLCRDivisors (mac_baseaddr , SlcrDiv0 , SlcrDiv1 );
590608 #endif
591609 }
592610 }
593-
594- /* SDT drivers should not write to the register */
595- #ifndef SDT
596- SlcrTxClkCntrl = * ( volatile unsigned int * ) ( slcrBaseAddress );
597- SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK ;
598- SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
599- SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
600- * ( volatile unsigned int * ) ( slcrBaseAddress ) = SlcrTxClkCntrl ;
601- #else
602- ( void ) SlcrTxClkCntrl ;
603- ( void ) SlcrDiv0 ;
604- ( void ) SlcrDiv1 ;
605- ( void ) slcrBaseAddress ;
606- #endif
607611 #endif /* ifdef PEEP */
608612 * ( volatile unsigned int * ) ( SLCR_LOCK_ADDR ) = SLCR_LOCK_KEY_VALUE ;
609613}
610614
611-
612615unsigned link_speed ;
613616unsigned Phy_Setup ( XEmacPs * xemacpsp )
614617{
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