Skip to content

Commit 1fdbdb8

Browse files
committed
[riscv] Convert a set of tests to opaque pointers
1 parent 71b4d74 commit 1fdbdb8

File tree

4 files changed

+88
-88
lines changed

4 files changed

+88
-88
lines changed

llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; RUN: llc -mtriple riscv64 -mattr=+v %s -o - \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

7-
define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vscale x 4 x i16> *%pb) nounwind {
7+
define void @vadd_vint16m1(ptr %pc, ptr %pa, ptr %pb) nounwind {
88
; CHECK-LABEL: vadd_vint16m1:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: vl1re16.v v8, (a1)
@@ -13,14 +13,14 @@ define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vs
1313
; CHECK-NEXT: vadd.vv v8, v8, v9
1414
; CHECK-NEXT: vs1r.v v8, (a0)
1515
; CHECK-NEXT: ret
16-
%va = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pa
17-
%vb = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pb
16+
%va = load <vscale x 4 x i16>, ptr %pa
17+
%vb = load <vscale x 4 x i16>, ptr %pb
1818
%vc = add <vscale x 4 x i16> %va, %vb
19-
store <vscale x 4 x i16> %vc, <vscale x 4 x i16> *%pc
19+
store <vscale x 4 x i16> %vc, ptr %pc
2020
ret void
2121
}
2222

23-
define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vscale x 8 x i16> *%pb) nounwind {
23+
define void @vadd_vint16m2(ptr %pc, ptr %pa, ptr %pb) nounwind {
2424
; CHECK-LABEL: vadd_vint16m2:
2525
; CHECK: # %bb.0:
2626
; CHECK-NEXT: vl2re16.v v8, (a1)
@@ -29,14 +29,14 @@ define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vs
2929
; CHECK-NEXT: vadd.vv v8, v8, v10
3030
; CHECK-NEXT: vs2r.v v8, (a0)
3131
; CHECK-NEXT: ret
32-
%va = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pa
33-
%vb = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pb
32+
%va = load <vscale x 8 x i16>, ptr %pa
33+
%vb = load <vscale x 8 x i16>, ptr %pb
3434
%vc = add <vscale x 8 x i16> %va, %vb
35-
store <vscale x 8 x i16> %vc, <vscale x 8 x i16> *%pc
35+
store <vscale x 8 x i16> %vc, ptr %pc
3636
ret void
3737
}
3838

39-
define void @vadd_vint16m4(<vscale x 16 x i16> *%pc, <vscale x 16 x i16> *%pa, <vscale x 16 x i16> *%pb) nounwind {
39+
define void @vadd_vint16m4(ptr %pc, ptr %pa, ptr %pb) nounwind {
4040
; CHECK-LABEL: vadd_vint16m4:
4141
; CHECK: # %bb.0:
4242
; CHECK-NEXT: vl4re16.v v8, (a1)
@@ -45,14 +45,14 @@ define void @vadd_vint16m4(<vscale x 16 x i16> *%pc, <vscale x 16 x i16> *%pa, <
4545
; CHECK-NEXT: vadd.vv v8, v8, v12
4646
; CHECK-NEXT: vs4r.v v8, (a0)
4747
; CHECK-NEXT: ret
48-
%va = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pa
49-
%vb = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pb
48+
%va = load <vscale x 16 x i16>, ptr %pa
49+
%vb = load <vscale x 16 x i16>, ptr %pb
5050
%vc = add <vscale x 16 x i16> %va, %vb
51-
store <vscale x 16 x i16> %vc, <vscale x 16 x i16> *%pc
51+
store <vscale x 16 x i16> %vc, ptr %pc
5252
ret void
5353
}
5454

55-
define void @vadd_vint16m8(<vscale x 32 x i16> *%pc, <vscale x 32 x i16> *%pa, <vscale x 32 x i16> *%pb) nounwind {
55+
define void @vadd_vint16m8(ptr %pc, ptr %pa, ptr %pb) nounwind {
5656
; CHECK-LABEL: vadd_vint16m8:
5757
; CHECK: # %bb.0:
5858
; CHECK-NEXT: vl8re16.v v8, (a1)
@@ -61,14 +61,14 @@ define void @vadd_vint16m8(<vscale x 32 x i16> *%pc, <vscale x 32 x i16> *%pa, <
6161
; CHECK-NEXT: vadd.vv v8, v8, v16
6262
; CHECK-NEXT: vs8r.v v8, (a0)
6363
; CHECK-NEXT: ret
64-
%va = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pa
65-
%vb = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pb
64+
%va = load <vscale x 32 x i16>, ptr %pa
65+
%vb = load <vscale x 32 x i16>, ptr %pb
6666
%vc = add <vscale x 32 x i16> %va, %vb
67-
store <vscale x 32 x i16> %vc, <vscale x 32 x i16> *%pc
67+
store <vscale x 32 x i16> %vc, ptr %pc
6868
ret void
6969
}
7070

71-
define void @vadd_vint16mf2(<vscale x 2 x i16> *%pc, <vscale x 2 x i16> *%pa, <vscale x 2 x i16> *%pb) nounwind {
71+
define void @vadd_vint16mf2(ptr %pc, ptr %pa, ptr %pb) nounwind {
7272
; CHECK-LABEL: vadd_vint16mf2:
7373
; CHECK: # %bb.0:
7474
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
@@ -77,14 +77,14 @@ define void @vadd_vint16mf2(<vscale x 2 x i16> *%pc, <vscale x 2 x i16> *%pa, <v
7777
; CHECK-NEXT: vadd.vv v8, v8, v9
7878
; CHECK-NEXT: vse16.v v8, (a0)
7979
; CHECK-NEXT: ret
80-
%va = load <vscale x 2 x i16>, <vscale x 2 x i16>* %pa
81-
%vb = load <vscale x 2 x i16>, <vscale x 2 x i16>* %pb
80+
%va = load <vscale x 2 x i16>, ptr %pa
81+
%vb = load <vscale x 2 x i16>, ptr %pb
8282
%vc = add <vscale x 2 x i16> %va, %vb
83-
store <vscale x 2 x i16> %vc, <vscale x 2 x i16> *%pc
83+
store <vscale x 2 x i16> %vc, ptr %pc
8484
ret void
8585
}
8686

87-
define void @vadd_vint16mf4(<vscale x 1 x i16> *%pc, <vscale x 1 x i16> *%pa, <vscale x 1 x i16> *%pb) nounwind {
87+
define void @vadd_vint16mf4(ptr %pc, ptr %pa, ptr %pb) nounwind {
8888
; CHECK-LABEL: vadd_vint16mf4:
8989
; CHECK: # %bb.0:
9090
; CHECK-NEXT: vsetvli a3, zero, e16, mf4, ta, ma
@@ -93,9 +93,9 @@ define void @vadd_vint16mf4(<vscale x 1 x i16> *%pc, <vscale x 1 x i16> *%pa, <v
9393
; CHECK-NEXT: vadd.vv v8, v8, v9
9494
; CHECK-NEXT: vse16.v v8, (a0)
9595
; CHECK-NEXT: ret
96-
%va = load <vscale x 1 x i16>, <vscale x 1 x i16>* %pa
97-
%vb = load <vscale x 1 x i16>, <vscale x 1 x i16>* %pb
96+
%va = load <vscale x 1 x i16>, ptr %pa
97+
%vb = load <vscale x 1 x i16>, ptr %pb
9898
%vc = add <vscale x 1 x i16> %va, %vb
99-
store <vscale x 1 x i16> %vc, <vscale x 1 x i16> *%pc
99+
store <vscale x 1 x i16> %vc, ptr %pc
100100
ret void
101101
}

llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; RUN: llc -mtriple riscv64 -mattr=+v %s -o - \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

7-
define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vscale x 2 x i32> *%pb) nounwind {
7+
define void @vadd_vint32m1(ptr %pc, ptr %pa, ptr %pb) nounwind {
88
; CHECK-LABEL: vadd_vint32m1:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: vl1re32.v v8, (a1)
@@ -13,14 +13,14 @@ define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vs
1313
; CHECK-NEXT: vadd.vv v8, v8, v9
1414
; CHECK-NEXT: vs1r.v v8, (a0)
1515
; CHECK-NEXT: ret
16-
%va = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pa
17-
%vb = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pb
16+
%va = load <vscale x 2 x i32>, ptr %pa
17+
%vb = load <vscale x 2 x i32>, ptr %pb
1818
%vc = add <vscale x 2 x i32> %va, %vb
19-
store <vscale x 2 x i32> %vc, <vscale x 2 x i32> *%pc
19+
store <vscale x 2 x i32> %vc, ptr %pc
2020
ret void
2121
}
2222

23-
define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vscale x 4 x i32> *%pb) nounwind {
23+
define void @vadd_vint32m2(ptr %pc, ptr %pa, ptr %pb) nounwind {
2424
; CHECK-LABEL: vadd_vint32m2:
2525
; CHECK: # %bb.0:
2626
; CHECK-NEXT: vl2re32.v v8, (a1)
@@ -29,14 +29,14 @@ define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vs
2929
; CHECK-NEXT: vadd.vv v8, v8, v10
3030
; CHECK-NEXT: vs2r.v v8, (a0)
3131
; CHECK-NEXT: ret
32-
%va = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pa
33-
%vb = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pb
32+
%va = load <vscale x 4 x i32>, ptr %pa
33+
%vb = load <vscale x 4 x i32>, ptr %pb
3434
%vc = add <vscale x 4 x i32> %va, %vb
35-
store <vscale x 4 x i32> %vc, <vscale x 4 x i32> *%pc
35+
store <vscale x 4 x i32> %vc, ptr %pc
3636
ret void
3737
}
3838

39-
define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vscale x 8 x i32> *%pb) nounwind {
39+
define void @vadd_vint32m4(ptr %pc, ptr %pa, ptr %pb) nounwind {
4040
; CHECK-LABEL: vadd_vint32m4:
4141
; CHECK: # %bb.0:
4242
; CHECK-NEXT: vl4re32.v v8, (a1)
@@ -45,14 +45,14 @@ define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vs
4545
; CHECK-NEXT: vadd.vv v8, v8, v12
4646
; CHECK-NEXT: vs4r.v v8, (a0)
4747
; CHECK-NEXT: ret
48-
%va = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pa
49-
%vb = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pb
48+
%va = load <vscale x 8 x i32>, ptr %pa
49+
%vb = load <vscale x 8 x i32>, ptr %pb
5050
%vc = add <vscale x 8 x i32> %va, %vb
51-
store <vscale x 8 x i32> %vc, <vscale x 8 x i32> *%pc
51+
store <vscale x 8 x i32> %vc, ptr %pc
5252
ret void
5353
}
5454

55-
define void @vadd_vint32m8(<vscale x 16 x i32> *%pc, <vscale x 16 x i32> *%pa, <vscale x 16 x i32> *%pb) nounwind {
55+
define void @vadd_vint32m8(ptr %pc, ptr %pa, ptr %pb) nounwind {
5656
; CHECK-LABEL: vadd_vint32m8:
5757
; CHECK: # %bb.0:
5858
; CHECK-NEXT: vl8re32.v v8, (a1)
@@ -61,14 +61,14 @@ define void @vadd_vint32m8(<vscale x 16 x i32> *%pc, <vscale x 16 x i32> *%pa, <
6161
; CHECK-NEXT: vadd.vv v8, v8, v16
6262
; CHECK-NEXT: vs8r.v v8, (a0)
6363
; CHECK-NEXT: ret
64-
%va = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pa
65-
%vb = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pb
64+
%va = load <vscale x 16 x i32>, ptr %pa
65+
%vb = load <vscale x 16 x i32>, ptr %pb
6666
%vc = add <vscale x 16 x i32> %va, %vb
67-
store <vscale x 16 x i32> %vc, <vscale x 16 x i32> *%pc
67+
store <vscale x 16 x i32> %vc, ptr %pc
6868
ret void
6969
}
7070

71-
define void @vadd_vint32mf2(<vscale x 1 x i32> *%pc, <vscale x 1 x i32> *%pa, <vscale x 1 x i32> *%pb) nounwind {
71+
define void @vadd_vint32mf2(ptr %pc, ptr %pa, ptr %pb) nounwind {
7272
; CHECK-LABEL: vadd_vint32mf2:
7373
; CHECK: # %bb.0:
7474
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
@@ -77,9 +77,9 @@ define void @vadd_vint32mf2(<vscale x 1 x i32> *%pc, <vscale x 1 x i32> *%pa, <v
7777
; CHECK-NEXT: vadd.vv v8, v8, v9
7878
; CHECK-NEXT: vse32.v v8, (a0)
7979
; CHECK-NEXT: ret
80-
%va = load <vscale x 1 x i32>, <vscale x 1 x i32>* %pa
81-
%vb = load <vscale x 1 x i32>, <vscale x 1 x i32>* %pb
80+
%va = load <vscale x 1 x i32>, ptr %pa
81+
%vb = load <vscale x 1 x i32>, ptr %pb
8282
%vc = add <vscale x 1 x i32> %va, %vb
83-
store <vscale x 1 x i32> %vc, <vscale x 1 x i32> *%pc
83+
store <vscale x 1 x i32> %vc, ptr %pc
8484
ret void
8585
}

llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; RUN: llc -mtriple riscv64 -mattr=+v %s -o - \
55
; RUN: -verify-machineinstrs | FileCheck %s
66

7-
define void @vadd_vint64m1(<vscale x 1 x i64> *%pc, <vscale x 1 x i64> *%pa, <vscale x 1 x i64> *%pb) nounwind {
7+
define void @vadd_vint64m1(ptr %pc, ptr %pa, ptr %pb) nounwind {
88
; CHECK-LABEL: vadd_vint64m1:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: vl1re64.v v8, (a1)
@@ -13,14 +13,14 @@ define void @vadd_vint64m1(<vscale x 1 x i64> *%pc, <vscale x 1 x i64> *%pa, <vs
1313
; CHECK-NEXT: vadd.vv v8, v8, v9
1414
; CHECK-NEXT: vs1r.v v8, (a0)
1515
; CHECK-NEXT: ret
16-
%va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa
17-
%vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb
16+
%va = load <vscale x 1 x i64>, ptr %pa
17+
%vb = load <vscale x 1 x i64>, ptr %pb
1818
%vc = add <vscale x 1 x i64> %va, %vb
19-
store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc
19+
store <vscale x 1 x i64> %vc, ptr %pc
2020
ret void
2121
}
2222

23-
define void @vadd_vint64m2(<vscale x 2 x i64> *%pc, <vscale x 2 x i64> *%pa, <vscale x 2 x i64> *%pb) nounwind {
23+
define void @vadd_vint64m2(ptr %pc, ptr %pa, ptr %pb) nounwind {
2424
; CHECK-LABEL: vadd_vint64m2:
2525
; CHECK: # %bb.0:
2626
; CHECK-NEXT: vl2re64.v v8, (a1)
@@ -29,14 +29,14 @@ define void @vadd_vint64m2(<vscale x 2 x i64> *%pc, <vscale x 2 x i64> *%pa, <vs
2929
; CHECK-NEXT: vadd.vv v8, v8, v10
3030
; CHECK-NEXT: vs2r.v v8, (a0)
3131
; CHECK-NEXT: ret
32-
%va = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pa
33-
%vb = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pb
32+
%va = load <vscale x 2 x i64>, ptr %pa
33+
%vb = load <vscale x 2 x i64>, ptr %pb
3434
%vc = add <vscale x 2 x i64> %va, %vb
35-
store <vscale x 2 x i64> %vc, <vscale x 2 x i64> *%pc
35+
store <vscale x 2 x i64> %vc, ptr %pc
3636
ret void
3737
}
3838

39-
define void @vadd_vint64m4(<vscale x 4 x i64> *%pc, <vscale x 4 x i64> *%pa, <vscale x 4 x i64> *%pb) nounwind {
39+
define void @vadd_vint64m4(ptr %pc, ptr %pa, ptr %pb) nounwind {
4040
; CHECK-LABEL: vadd_vint64m4:
4141
; CHECK: # %bb.0:
4242
; CHECK-NEXT: vl4re64.v v8, (a1)
@@ -45,14 +45,14 @@ define void @vadd_vint64m4(<vscale x 4 x i64> *%pc, <vscale x 4 x i64> *%pa, <vs
4545
; CHECK-NEXT: vadd.vv v8, v8, v12
4646
; CHECK-NEXT: vs4r.v v8, (a0)
4747
; CHECK-NEXT: ret
48-
%va = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pa
49-
%vb = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pb
48+
%va = load <vscale x 4 x i64>, ptr %pa
49+
%vb = load <vscale x 4 x i64>, ptr %pb
5050
%vc = add <vscale x 4 x i64> %va, %vb
51-
store <vscale x 4 x i64> %vc, <vscale x 4 x i64> *%pc
51+
store <vscale x 4 x i64> %vc, ptr %pc
5252
ret void
5353
}
5454

55-
define void @vadd_vint64m8(<vscale x 8 x i64> *%pc, <vscale x 8 x i64> *%pa, <vscale x 8 x i64> *%pb) nounwind {
55+
define void @vadd_vint64m8(ptr %pc, ptr %pa, ptr %pb) nounwind {
5656
; CHECK-LABEL: vadd_vint64m8:
5757
; CHECK: # %bb.0:
5858
; CHECK-NEXT: vl8re64.v v8, (a1)
@@ -61,9 +61,9 @@ define void @vadd_vint64m8(<vscale x 8 x i64> *%pc, <vscale x 8 x i64> *%pa, <vs
6161
; CHECK-NEXT: vadd.vv v8, v8, v16
6262
; CHECK-NEXT: vs8r.v v8, (a0)
6363
; CHECK-NEXT: ret
64-
%va = load <vscale x 8 x i64>, <vscale x 8 x i64>* %pa
65-
%vb = load <vscale x 8 x i64>, <vscale x 8 x i64>* %pb
64+
%va = load <vscale x 8 x i64>, ptr %pa
65+
%vb = load <vscale x 8 x i64>, ptr %pb
6666
%vc = add <vscale x 8 x i64> %va, %vb
67-
store <vscale x 8 x i64> %vc, <vscale x 8 x i64> *%pc
67+
store <vscale x 8 x i64> %vc, ptr %pc
6868
ret void
6969
}

0 commit comments

Comments
 (0)