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Merged main:9b83ffb5c609 into origin/amd-gfx:05dcc8ead824
Local branch origin/amd-gfx 05dcc8e Merged main:2a48995a03ca into origin/amd-gfx:9e52601fabfa Remote branch main 9b83ffb AMDGPU: Switch a test to generated checks which only tested labels (llvm#131257)
2 parents 05dcc8e + 9b83ffb commit 275fb31

38 files changed

+689
-338
lines changed

‎clang/lib/Format/Format.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1713,6 +1713,10 @@ FormatStyle getGoogleStyle(FormatStyle::LanguageKind Language) {
17131713
FormatStyle::SIS_WithoutElse;
17141714
GoogleStyle.AllowShortLoopsOnASingleLine = true;
17151715
GoogleStyle.AlwaysBreakBeforeMultilineStrings = true;
1716+
// Abseil aliases to clang's `_Nonnull`, `_Nullable` and `_Null_unspecified`.
1717+
GoogleStyle.AttributeMacros.push_back("absl_nonnull");
1718+
GoogleStyle.AttributeMacros.push_back("absl_nullable");
1719+
GoogleStyle.AttributeMacros.push_back("absl_nullability_unknown");
17161720
GoogleStyle.BreakTemplateDeclarations = FormatStyle::BTDS_Yes;
17171721
GoogleStyle.DerivePointerAlignment = true;
17181722
GoogleStyle.IncludeStyle.IncludeBlocks = tooling::IncludeStyle::IBS_Regroup;

‎clang/unittests/Format/ConfigParseTest.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -909,6 +909,11 @@ TEST(ConfigParseTest, ParsesConfiguration) {
909909
Style.AttributeMacros.clear();
910910
CHECK_PARSE("BasedOnStyle: LLVM", AttributeMacros,
911911
std::vector<std::string>{"__capability"});
912+
CHECK_PARSE(
913+
"BasedOnStyle: Google", AttributeMacros,
914+
std::vector<std::string>({"__capability", "absl_nonnull", "absl_nullable",
915+
"absl_nullability_unknown"}));
916+
Style.AttributeMacros.clear();
912917
CHECK_PARSE("AttributeMacros: [attr1, attr2]", AttributeMacros,
913918
std::vector<std::string>({"attr1", "attr2"}));
914919

‎clang/unittests/Format/FormatTest.cpp

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12375,6 +12375,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
1237512375
verifyFormat("vector<a *_Nonnull> v;");
1237612376
verifyFormat("vector<a *_Nullable> v;");
1237712377
verifyFormat("vector<a *_Null_unspecified> v;");
12378+
verifyGoogleFormat("vector<a* absl_nonnull> v;");
12379+
verifyGoogleFormat("vector<a* absl_nullable> v;");
12380+
verifyGoogleFormat("vector<a* absl_nullability_unknown> v;");
1237812381
verifyFormat("vector<a *__ptr32> v;");
1237912382
verifyFormat("vector<a *__ptr64> v;");
1238012383
verifyFormat("vector<a *__capability> v;");
@@ -12518,6 +12521,12 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
1251812521
verifyIndependentOfContext("MACRO(A *_Nonnull a);");
1251912522
verifyIndependentOfContext("MACRO(A *_Nullable a);");
1252012523
verifyIndependentOfContext("MACRO(A *_Null_unspecified a);");
12524+
12525+
Style = getGoogleStyle();
12526+
verifyIndependentOfContext("MACRO(A* absl_nonnull a);", Style);
12527+
verifyIndependentOfContext("MACRO(A* absl_nullable a);", Style);
12528+
verifyIndependentOfContext("MACRO(A* absl_nullability_unknown a);", Style);
12529+
1252112530
verifyIndependentOfContext("MACRO(A *__attribute__((foo)) a);");
1252212531
verifyIndependentOfContext("MACRO(A *__attribute((foo)) a);");
1252312532
verifyIndependentOfContext("MACRO(A *[[clang::attr]] a);");
@@ -12676,6 +12685,12 @@ TEST_F(FormatTest, UnderstandsAttributes) {
1267612685
verifyFormat("SomeType s __unused{InitValue};", CustomAttrs);
1267712686
verifyFormat("SomeType *__capability s(InitValue);", CustomAttrs);
1267812687
verifyFormat("SomeType *__capability s{InitValue};", CustomAttrs);
12688+
verifyGoogleFormat("SomeType* absl_nonnull s(InitValue);");
12689+
verifyGoogleFormat("SomeType* absl_nonnull s{InitValue};");
12690+
verifyGoogleFormat("SomeType* absl_nullable s(InitValue);");
12691+
verifyGoogleFormat("SomeType* absl_nullable s{InitValue};");
12692+
verifyGoogleFormat("SomeType* absl_nullability_unknown s(InitValue);");
12693+
verifyGoogleFormat("SomeType* absl_nullability_unknown s{InitValue};");
1267912694
}
1268012695

1268112696
TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
@@ -12687,7 +12702,9 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
1268712702
verifyFormat("x = (foo *_Nonnull)*v;");
1268812703
verifyFormat("x = (foo *_Nullable)*v;");
1268912704
verifyFormat("x = (foo *_Null_unspecified)*v;");
12690-
verifyFormat("x = (foo *_Nonnull)*v;");
12705+
verifyGoogleFormat("x = (foo* absl_nonnull)*v;");
12706+
verifyGoogleFormat("x = (foo* absl_nullable)*v;");
12707+
verifyGoogleFormat("x = (foo* absl_nullability_unknown)*v;");
1269112708
verifyFormat("x = (foo *[[clang::attr]])*v;");
1269212709
verifyFormat("x = (foo *[[clang::attr(\"foo\")]])*v;");
1269312710
verifyFormat("x = (foo *__ptr32)*v;");
@@ -12701,7 +12718,7 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
1270112718
LongPointerLeft.PointerAlignment = FormatStyle::PAS_Left;
1270212719
StringRef AllQualifiers =
1270312720
"const volatile restrict __attribute__((foo)) _Nonnull _Null_unspecified "
12704-
"_Nonnull [[clang::attr]] __ptr32 __ptr64 __capability";
12721+
"_Nullable [[clang::attr]] __ptr32 __ptr64 __capability";
1270512722
verifyFormat(("x = (foo *" + AllQualifiers + ")*v;").str(), LongPointerRight);
1270612723
verifyFormat(("x = (foo* " + AllQualifiers + ")*v;").str(), LongPointerLeft);
1270712724

‎clang/unittests/Format/TokenAnnotatorTest.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3185,6 +3185,29 @@ TEST_F(TokenAnnotatorTest, UnderstandsAttributes) {
31853185
EXPECT_TOKEN(Tokens[5], tok::r_paren, TT_AttributeRParen);
31863186
}
31873187

3188+
TEST_F(TokenAnnotatorTest, UnderstandsNullabilityAttributeMacros) {
3189+
// Under Google style, handles the Abseil macro aliases for the Clang
3190+
// nullability annotations.
3191+
auto Style = getGoogleStyle(FormatStyle::LK_Cpp);
3192+
auto Tokens = annotate("x = (foo* absl_nullable)*v;", Style);
3193+
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
3194+
EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
3195+
EXPECT_TOKEN(Tokens[5], tok::identifier, TT_AttributeMacro);
3196+
EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
3197+
3198+
Tokens = annotate("x = (foo* absl_nonnull)*v;", Style);
3199+
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
3200+
EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
3201+
EXPECT_TOKEN(Tokens[5], tok::identifier, TT_AttributeMacro);
3202+
EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
3203+
3204+
Tokens = annotate("x = (foo* absl_nullability_unknown)*v;", Style);
3205+
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
3206+
EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
3207+
EXPECT_TOKEN(Tokens[5], tok::identifier, TT_AttributeMacro);
3208+
EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
3209+
}
3210+
31883211
TEST_F(TokenAnnotatorTest, UnderstandsControlStatements) {
31893212
auto Tokens = annotate("while (true) {}");
31903213
ASSERT_EQ(Tokens.size(), 7u) << Tokens;

‎lldb/source/Core/Disassembler.cpp

Lines changed: 29 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -552,28 +552,46 @@ void Disassembler::PrintInstructions(Debugger &debugger, const ArchSpec &arch,
552552

553553
bool Disassembler::Disassemble(Debugger &debugger, const ArchSpec &arch,
554554
StackFrame &frame, Stream &strm) {
555-
AddressRange range;
555+
constexpr const char *plugin_name = nullptr;
556+
constexpr const char *flavor = nullptr;
557+
constexpr const char *cpu = nullptr;
558+
constexpr const char *features = nullptr;
559+
constexpr bool mixed_source_and_assembly = false;
560+
constexpr uint32_t num_mixed_context_lines = 0;
561+
constexpr uint32_t options = 0;
562+
556563
SymbolContext sc(
557564
frame.GetSymbolContext(eSymbolContextFunction | eSymbolContextSymbol));
558565
if (sc.function) {
559-
range = sc.function->GetAddressRange();
560-
} else if (sc.symbol && sc.symbol->ValueIsAddress()) {
566+
if (DisassemblerSP disasm_sp = DisassembleRange(
567+
arch, plugin_name, flavor, cpu, features, *frame.CalculateTarget(),
568+
sc.function->GetAddressRanges())) {
569+
disasm_sp->PrintInstructions(debugger, arch, frame,
570+
mixed_source_and_assembly,
571+
num_mixed_context_lines, options, strm);
572+
return true;
573+
}
574+
return false;
575+
}
576+
577+
AddressRange range;
578+
if (sc.symbol && sc.symbol->ValueIsAddress()) {
561579
range.GetBaseAddress() = sc.symbol->GetAddressRef();
562580
range.SetByteSize(sc.symbol->GetByteSize());
563581
} else {
564582
range.GetBaseAddress() = frame.GetFrameCodeAddress();
565583
}
566584

567-
if (range.GetBaseAddress().IsValid() && range.GetByteSize() == 0)
568-
range.SetByteSize(DEFAULT_DISASM_BYTE_SIZE);
585+
if (range.GetBaseAddress().IsValid() && range.GetByteSize() == 0)
586+
range.SetByteSize(DEFAULT_DISASM_BYTE_SIZE);
569587

570-
Disassembler::Limit limit = {Disassembler::Limit::Bytes,
571-
range.GetByteSize()};
572-
if (limit.value == 0)
573-
limit.value = DEFAULT_DISASM_BYTE_SIZE;
588+
Disassembler::Limit limit = {Disassembler::Limit::Bytes, range.GetByteSize()};
589+
if (limit.value == 0)
590+
limit.value = DEFAULT_DISASM_BYTE_SIZE;
574591

575-
return Disassemble(debugger, arch, nullptr, nullptr, nullptr, nullptr,
576-
frame, range.GetBaseAddress(), limit, false, 0, 0, strm);
592+
return Disassemble(debugger, arch, plugin_name, flavor, cpu, features, frame,
593+
range.GetBaseAddress(), limit, mixed_source_and_assembly,
594+
num_mixed_context_lines, options, strm);
577595
}
578596

579597
Instruction::Instruction(const Address &address, AddressClass addr_class)

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,7 +1306,7 @@ class TargetInstrInfo : public MCInstrInfo {
13061306
MachineInstr &Root, unsigned Pattern,
13071307
SmallVectorImpl<MachineInstr *> &InsInstrs,
13081308
SmallVectorImpl<MachineInstr *> &DelInstrs,
1309-
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1309+
DenseMap<Register, unsigned> &InstIdxForVirtReg) const;
13101310

13111311
/// When calculate the latency of the root instruction, accumulate the
13121312
/// latency of the sequence to the root latency.
@@ -1329,7 +1329,7 @@ class TargetInstrInfo : public MCInstrInfo {
13291329
SmallVectorImpl<MachineInstr *> &InsInstrs,
13301330
SmallVectorImpl<MachineInstr *> &DelInstrs,
13311331
ArrayRef<unsigned> OperandIndices,
1332-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1332+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const;
13331333

13341334
/// Reassociation of some instructions requires inverse operations (e.g.
13351335
/// (X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 530602
19+
#define LLVM_MAIN_REVISION 530612
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/lib/CodeGen/MachineCombiner.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ class MachineCombiner : public MachineFunctionPass {
9191
MachineInstr *getOperandDef(const MachineOperand &MO);
9292
bool isTransientMI(const MachineInstr *MI);
9393
unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
94-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
94+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
9595
MachineTraceMetrics::Trace BlockTrace,
9696
const MachineBasicBlock &MBB);
9797
unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
@@ -100,7 +100,7 @@ class MachineCombiner : public MachineFunctionPass {
100100
MachineTraceMetrics::Trace BlockTrace,
101101
SmallVectorImpl<MachineInstr *> &InsInstrs,
102102
SmallVectorImpl<MachineInstr *> &DelInstrs,
103-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
103+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
104104
unsigned Pattern, bool SlackIsAccurate);
105105
bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
106106
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -202,7 +202,7 @@ bool MachineCombiner::isTransientMI(const MachineInstr *MI) {
202202
/// \returns Depth of last instruction in \InsInstrs ("NewRoot")
203203
unsigned
204204
MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
205-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
205+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
206206
MachineTraceMetrics::Trace BlockTrace,
207207
const MachineBasicBlock &MBB) {
208208
SmallVector<unsigned, 16> InstrDepth;
@@ -217,7 +217,7 @@ MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
217217
continue;
218218
unsigned DepthOp = 0;
219219
unsigned LatencyOp = 0;
220-
DenseMap<unsigned, unsigned>::iterator II =
220+
DenseMap<Register, unsigned>::iterator II =
221221
InstrIdxForVirtReg.find(MO.getReg());
222222
if (II != InstrIdxForVirtReg.end()) {
223223
// Operand is new virtual register not in trace
@@ -353,7 +353,7 @@ bool MachineCombiner::improvesCriticalPathLen(
353353
MachineTraceMetrics::Trace BlockTrace,
354354
SmallVectorImpl<MachineInstr *> &InsInstrs,
355355
SmallVectorImpl<MachineInstr *> &DelInstrs,
356-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned Pattern,
356+
DenseMap<Register, unsigned> &InstrIdxForVirtReg, unsigned Pattern,
357357
bool SlackIsAccurate) {
358358
// Get depth and latency of NewRoot and Root.
359359
unsigned NewRootDepth =
@@ -527,7 +527,7 @@ void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB,
527527
for (auto P : Patterns) {
528528
SmallVector<MachineInstr *, 16> InsInstrs;
529529
SmallVector<MachineInstr *, 16> DelInstrs;
530-
DenseMap<unsigned, unsigned> InstrIdxForVirtReg;
530+
DenseMap<Register, unsigned> InstrIdxForVirtReg;
531531
TII->genAlternativeCodeSequence(Root, P, InsInstrs, DelInstrs,
532532
InstrIdxForVirtReg);
533533
// Found pattern, but did not generate alternative sequence.
@@ -612,7 +612,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
612612
for (const auto P : Patterns) {
613613
SmallVector<MachineInstr *, 16> InsInstrs;
614614
SmallVector<MachineInstr *, 16> DelInstrs;
615-
DenseMap<unsigned, unsigned> InstrIdxForVirtReg;
615+
DenseMap<Register, unsigned> InstrIdxForVirtReg;
616616
TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs,
617617
InstrIdxForVirtReg);
618618
// Found pattern, but did not generate alternative sequence.

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1085,7 +1085,7 @@ void TargetInstrInfo::reassociateOps(
10851085
SmallVectorImpl<MachineInstr *> &InsInstrs,
10861086
SmallVectorImpl<MachineInstr *> &DelInstrs,
10871087
ArrayRef<unsigned> OperandIndices,
1088-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
1088+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
10891089
MachineFunction *MF = Root.getMF();
10901090
MachineRegisterInfo &MRI = MF->getRegInfo();
10911091
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
@@ -1250,7 +1250,7 @@ void TargetInstrInfo::genAlternativeCodeSequence(
12501250
MachineInstr &Root, unsigned Pattern,
12511251
SmallVectorImpl<MachineInstr *> &InsInstrs,
12521252
SmallVectorImpl<MachineInstr *> &DelInstrs,
1253-
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
1253+
DenseMap<Register, unsigned> &InstIdxForVirtReg) const {
12541254
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
12551255

12561256
// Select the previous instruction in the sequence based on the input pattern.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7360,7 +7360,7 @@ static MachineInstr *genFusedMultiplyAcc(
73607360
static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI,
73617361
const TargetInstrInfo *TII, MachineInstr &Root,
73627362
SmallVectorImpl<MachineInstr *> &InsInstrs,
7363-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
7363+
DenseMap<Register, unsigned> &InstrIdxForVirtReg,
73647364
unsigned MnegOpc, const TargetRegisterClass *RC) {
73657365
Register NewVR = MRI.createVirtualRegister(RC);
73667366
MachineInstrBuilder MIB =
@@ -7379,7 +7379,7 @@ static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI,
73797379
static MachineInstr *genFusedMultiplyAccNeg(
73807380
MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
73817381
MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
7382-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
7382+
DenseMap<Register, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
73837383
unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) {
73847384
assert(IdxMulOpd == 1);
73857385

@@ -7406,7 +7406,7 @@ static MachineInstr *genFusedMultiplyIdx(
74067406
static MachineInstr *genFusedMultiplyIdxNeg(
74077407
MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII,
74087408
MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
7409-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
7409+
DenseMap<Register, unsigned> &InstrIdxForVirtReg, unsigned IdxMulOpd,
74107410
unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC) {
74117411
assert(IdxMulOpd == 1);
74127412

@@ -7472,13 +7472,12 @@ static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
74727472
/// Do the following transformation
74737473
/// A - (B + C) ==> (A - B) - C
74747474
/// A - (B + C) ==> (A - C) - B
7475-
static void
7476-
genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
7477-
const TargetInstrInfo *TII, MachineInstr &Root,
7478-
SmallVectorImpl<MachineInstr *> &InsInstrs,
7479-
SmallVectorImpl<MachineInstr *> &DelInstrs,
7480-
unsigned IdxOpd1,
7481-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
7475+
static void genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
7476+
const TargetInstrInfo *TII, MachineInstr &Root,
7477+
SmallVectorImpl<MachineInstr *> &InsInstrs,
7478+
SmallVectorImpl<MachineInstr *> &DelInstrs,
7479+
unsigned IdxOpd1,
7480+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
74827481
assert(IdxOpd1 == 1 || IdxOpd1 == 2);
74837482
unsigned IdxOtherOpd = IdxOpd1 == 1 ? 2 : 1;
74847483
MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
@@ -7531,7 +7530,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
75317530
MachineInstr &Root, unsigned Pattern,
75327531
SmallVectorImpl<MachineInstr *> &InsInstrs,
75337532
SmallVectorImpl<MachineInstr *> &DelInstrs,
7534-
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
7533+
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
75357534
MachineBasicBlock &MBB = *Root.getParent();
75367535
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
75377536
MachineFunction &MF = *MBB.getParent();

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