Merged main:b9a02765504f8b83701ffffc097531638c4fc22e into amd-gfx:3906fefcb801

Local branch amd-gfx 3906fef Merged main:77fccb35ac08f66d52bb152735e27572bf9f3f93 into amd-gfx:08f1863d2644
Remote branch main b9a0276 [ARM] Add VECTOR_REG_CAST identity fold.

Author: SC llvm team

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 509546
+#define LLVM_MAIN_REVISION 509547
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -15444,6 +15444,9 @@ static SDValue PerformVECTOR_REG_CASTCombine(SDNode *N, SelectionDAG &DAG,
   if (ST->isLittle())
     return DAG.getNode(ISD::BITCAST, dl, VT, Op);
 
+  // VT VECTOR_REG_CAST (VT Op) -> Op
+  if (Op.getValueType() == VT)
+    return Op;
   // VECTOR_REG_CAST undef -> undef
   if (Op.isUndef())
     return DAG.getUNDEF(VT);

llvm/test/CodeGen/Thumb2/mve-be.ll

@@ -278,10 +278,9 @@ define arm_aapcs_vfpcc <4 x i32> @test(ptr %data) {
 ;
 ; CHECK-BE-LABEL: test:
 ; CHECK-BE:       @ %bb.0: @ %entry
-; CHECK-BE-NEXT:    movs r1, #1
-; CHECK-BE-NEXT:    vldrw.u32 q1, [r0, #32]
-; CHECK-BE-NEXT:    vdup.32 q0, r1
-; CHECK-BE-NEXT:    vadd.i32 q0, q1, q0
+; CHECK-BE-NEXT:    vldrw.u32 q0, [r0, #32]
+; CHECK-BE-NEXT:    movs r0, #1
+; CHECK-BE-NEXT:    vadd.i32 q0, q0, r0
 ; CHECK-BE-NEXT:    vrev32.8 q0, q0
 ; CHECK-BE-NEXT:    @APP
 ; CHECK-BE-NEXT:    vmullb.s32 q1, q0, q0