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jerryyiransunarsenm
jerryyiransun
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arsenm
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[TableGen] [NFC] Refine TableGen code to comply with clang-tidy checks (llvm#113318)
Code cleanups for TableGen files, changes includes function names, variable names and unused imports. --------- Co-authored-by: Matt Arsenault <[email protected]>
1 parent 6563ed3 commit cdacc9b

15 files changed

+493
-493
lines changed

‎llvm/utils/TableGen/ARMTargetDefEmitter.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -25,19 +25,19 @@
2525
using namespace llvm;
2626

2727
/// Collect the full set of implied features for a SubtargetFeature.
28-
static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
28+
static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
2929
const Record *Rec) {
3030
assert(Rec->isSubClassOf("SubtargetFeature") &&
3131
"Rec is not a SubtargetFeature");
3232

3333
SeenFeats.insert(Rec);
3434
for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
35-
CollectImpliedFeatures(SeenFeats, Implied);
35+
collectImpliedFeatures(SeenFeats, Implied);
3636
}
3737

38-
static void CheckFeatureTree(const Record *Root) {
38+
static void checkFeatureTree(const Record *Root) {
3939
std::set<const Record *> SeenFeats;
40-
CollectImpliedFeatures(SeenFeats, Root);
40+
collectImpliedFeatures(SeenFeats, Root);
4141

4242
// Check that each of the mandatory (implied) features which is an
4343
// ExtensionWithMArch is also enabled by default.
@@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
5353
}
5454
}
5555

56-
static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
56+
static void emitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
5757
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
5858

5959
// Look through all SubtargetFeature defs with the given FieldName, and
6060
// collect the set of all Values that that FieldName is set to.
61-
auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
61+
auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
6262
llvm::StringSet<> Set;
6363
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
6464
if (Rec->getValueAsString("FieldName") == FieldName) {
@@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
8888
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
8989
<< "#endif\n\n";
9090
const StringSet<> ARMProcFamilyVals =
91-
gatherSubtargetFeatureFieldValues("ARMProcFamily");
91+
GatherSubtargetFeatureFieldValues("ARMProcFamily");
9292
for (const StringRef &Family : ARMProcFamilyVals.keys())
9393
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
9494
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
@@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
9797
<< "#define ARM_ARCHITECTURE(ENUM)\n"
9898
<< "#endif\n\n";
9999
// This should correspond to instances of the Architecture tablegen class.
100-
const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
100+
const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
101101
for (const StringRef &Arch : ARMArchVals.keys())
102102
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
103103
OS << "\n#undef ARM_ARCHITECTURE\n\n";
@@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
315315
auto Profile = Arch->getValueAsString("Profile");
316316
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
317317

318-
CheckFeatureTree(Arch);
318+
checkFeatureTree(Arch);
319319

320320
OS << " {\n"
321321
<< " \"" << Name << "\",\n"
@@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
343343
}
344344

345345
static TableGen::Emitter::Opt
346-
X("gen-arm-target-def", EmitARMTargetDef,
346+
X("gen-arm-target-def", emitARMTargetDef,
347347
"Generate the ARM or AArch64 Architecture information header.");

‎llvm/utils/TableGen/CallingConvEmitter.cpp‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -35,12 +35,12 @@ class CallingConvEmitter {
3535
public:
3636
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
3737

38-
void run(raw_ostream &o);
38+
void run(raw_ostream &O);
3939

4040
private:
41-
void EmitCallingConv(const Record *CC, raw_ostream &O);
42-
void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
43-
void EmitArgRegisterLists(raw_ostream &O);
41+
void emitCallingConv(const Record *CC, raw_ostream &O);
42+
void emitAction(const Record *Action, indent Indent, raw_ostream &O);
43+
void emitArgRegisterLists(raw_ostream &O);
4444
};
4545
} // End anonymous namespace
4646

@@ -75,16 +75,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
7575
Records.getTimer().startTimer("Emit full descriptions");
7676
for (const Record *CC : CCs) {
7777
if (!CC->getValueAsBit("Custom")) {
78-
EmitCallingConv(CC, O);
78+
emitCallingConv(CC, O);
7979
}
8080
}
8181

82-
EmitArgRegisterLists(O);
82+
emitArgRegisterLists(O);
8383

8484
O << "\n#endif // CC_REGISTER_LIST\n";
8585
}
8686

87-
void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
87+
void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
8888
const ListInit *CCActions = CC->getValueAsListInit("Actions");
8989
Counter = 0;
9090

@@ -107,8 +107,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
107107
<< std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
108108
<< std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
109109
// Emit all of the actions, in order.
110-
for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
111-
const Record *Action = CCActions->getElementAsRecord(i);
110+
for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
111+
const Record *Action = CCActions->getElementAsRecord(I);
112112
SwiftAction =
113113
llvm::any_of(Action->getSuperClasses(),
114114
[](const std::pair<const Record *, SMRange> &Class) {
@@ -117,23 +117,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
117117
});
118118

119119
O << "\n";
120-
EmitAction(Action, indent(2), O);
120+
emitAction(Action, indent(2), O);
121121
}
122122

123123
O << "\n return true; // CC didn't match.\n";
124124
O << "}\n";
125125
}
126126

127-
void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
127+
void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
128128
raw_ostream &O) {
129129
if (Action->isSubClassOf("CCPredicateAction")) {
130130
O << Indent << "if (";
131131

132132
if (Action->isSubClassOf("CCIfType")) {
133133
const ListInit *VTs = Action->getValueAsListInit("VTs");
134-
for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
135-
const Record *VT = VTs->getElementAsRecord(i);
136-
if (i != 0)
134+
for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
135+
const Record *VT = VTs->getElementAsRecord(I);
136+
if (I != 0)
137137
O << " ||\n " << Indent;
138138
O << "LocVT == " << getEnumName(getValueType(VT));
139139
}
@@ -146,7 +146,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
146146
}
147147

148148
O << ") {\n";
149-
EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
149+
emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
150150
O << Indent << "}\n";
151151
} else {
152152
if (Action->isSubClassOf("CCDelegateTo")) {
@@ -171,8 +171,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
171171
<< "[] = {\n";
172172
O << Indent << " ";
173173
ListSeparator LS;
174-
for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
175-
std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
174+
for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
175+
std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
176176
if (SwiftAction)
177177
AssignedSwiftRegsMap[CurrentAction].insert(Name);
178178
else
@@ -230,16 +230,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
230230
<< "[] = {\n";
231231
O << Indent << " ";
232232
ListSeparator LS;
233-
for (unsigned i = 0, e = RegList->size(); i != e; ++i)
234-
O << LS << getQualifiedName(RegList->getElementAsRecord(i));
233+
for (unsigned I = 0, E = RegList->size(); I != E; ++I)
234+
O << LS << getQualifiedName(RegList->getElementAsRecord(I));
235235
O << "\n" << Indent << "};\n";
236236

237237
O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
238238
<< "[] = {\n";
239239
O << Indent << " ";
240240
ListSeparator LSS;
241-
for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
242-
O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
241+
for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
242+
O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
243243
O << "\n" << Indent << "};\n";
244244

245245
O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
@@ -287,8 +287,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
287287
<< ShadowRegListNumber << "[] = {\n";
288288
O << Indent << " ";
289289
ListSeparator LS;
290-
for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
291-
O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
290+
for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
291+
O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
292292
O << "\n" << Indent << "};\n";
293293

294294
O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
@@ -357,7 +357,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
357357
}
358358
}
359359

360-
void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
360+
void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
361361
// Transitively merge all delegated CCs into AssignedRegsMap.
362362
using EntryTy = std::pair<std::string, std::set<std::string>>;
363363
bool Redo;

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