Skip to content

Commit 188a7ce

Browse files
hujun260xiaoxiang781216
hujun260
authored and
xiaoxiang781216
committed
gpio: use small lock to protect configgpio
reason: We would like to replace the critical section with a small lock. Signed-off-by: hujun5 <[email protected]>
1 parent 4a71421 commit 188a7ce

File tree

24 files changed

+182
-56
lines changed

24 files changed

+182
-56
lines changed

‎arch/arm/src/at32/at32_gpio.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,19 @@
3232
#include <errno.h>
3333
#include <debug.h>
3434
#include <nuttx/irq.h>
35+
#include <nuttx/spinlock.h>
3536

3637
#include "arm_internal.h"
3738
#include "chip.h"
3839
#include "at32_syscfg.h"
3940
#include "at32_gpio.h"
4041

42+
/****************************************************************************
43+
* Private Data
44+
****************************************************************************/
45+
46+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
47+
4148
/****************************************************************************
4249
* Public Data
4350
****************************************************************************/
@@ -199,7 +206,7 @@ int at32_configgpio(uint32_t cfgset)
199206
* exclusive access to all of the GPIO configuration registers.
200207
*/
201208

202-
flags = enter_critical_section();
209+
flags = spin_lock_irqsave(&g_configgpio_lock);
203210

204211
/* Determine the alternate function (Only alternate function pins) */
205212

@@ -355,7 +362,7 @@ int at32_configgpio(uint32_t cfgset)
355362
putreg32(regval, regaddr);
356363
}
357364

358-
leave_critical_section(flags);
365+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
359366
return OK;
360367
}
361368
#endif

‎arch/arm/src/eoss3/eoss3_gpio.c

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929

3030
#include <arch/board/board.h>
3131
#include <nuttx/irq.h>
32+
#include <nuttx/spinlock.h>
3233

3334
#include "arm_internal.h"
3435
#include "chip.h"
@@ -57,6 +58,8 @@
5758
* Private Data
5859
****************************************************************************/
5960

61+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
62+
6063
/****************************************************************************
6164
* Private Functions
6265
****************************************************************************/
@@ -82,7 +85,7 @@ int eoss3_configgpio(gpio_pinset_t cfgset)
8285
uint16_t sel_idx = \
8386
(input & EOSS3_PAD_SEL_IDX_MASK) >> EOSS3_PAD_SEL_IDX_SHIFT;
8487

85-
irqstate_t flags = enter_critical_section();
88+
irqstate_t flags = spin_lock_irqsave(&g_configgpio_lock);
8689

8790
/* Check select index, if it is 0 we are not working with an input */
8891

@@ -111,7 +114,7 @@ int eoss3_configgpio(gpio_pinset_t cfgset)
111114
}
112115

113116
putreg32(ctrl, EOSS3_PAD_X_CTRL(pad));
114-
leave_critical_section(flags);
117+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
115118
return OK;
116119
}
117120

@@ -141,7 +144,7 @@ void eoss3_gpiowrite(gpio_pinset_t cfgset, bool value)
141144
uint8_t iobit = (cfgset & GPIO_REG_BIT_MASK) >> GPIO_REG_BIT_SHIFT;
142145
if (cfgset & GPIO_REG_EN_MASK)
143146
{
144-
irqstate_t flags = enter_critical_section();
147+
irqstate_t flags = spin_lock_irqsave(&g_configgpio_lock);
145148
if (value)
146149
{
147150
putreg32(
@@ -155,7 +158,7 @@ void eoss3_gpiowrite(gpio_pinset_t cfgset, bool value)
155158
EOSS3_MISC_IO_OUTPUT);
156159
}
157160

158-
leave_critical_section(flags);
161+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
159162
}
160163
}
161164

‎arch/arm/src/nuc1xx/nuc_gpio.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#include <debug.h>
3232

3333
#include <nuttx/irq.h>
34+
#include <nuttx/spinlock.h>
3435
#include <arch/nuc1xx/chip.h>
3536

3637
#include "arm_internal.h"
@@ -43,6 +44,12 @@
4344
* Pre-processor Definitions
4445
****************************************************************************/
4546

47+
/****************************************************************************
48+
* Private Data
49+
****************************************************************************/
50+
51+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
52+
4653
/****************************************************************************
4754
* Private Functions
4855
****************************************************************************/
@@ -240,7 +247,7 @@ void nuc_gpiowrite(gpio_cfgset_t pinset, bool value)
240247

241248
/* Disable interrupts -- the following operations must be atomic */
242249

243-
flags = enter_critical_section();
250+
flags = spin_lock_irqsave(&g_configgpio_lock);
244251

245252
/* Allow writing only to the selected pin in the DOUT register */
246253

@@ -249,7 +256,7 @@ void nuc_gpiowrite(gpio_cfgset_t pinset, bool value)
249256
/* Set the pin to the selected value and re-enable interrupts */
250257

251258
putreg32(((uint32_t)value << pin), base + NUC_GPIO_DOUT_OFFSET);
252-
leave_critical_section(flags);
259+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
253260
#endif
254261
}
255262

‎arch/arm/src/sam34/sam4l_gpio.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333

3434
#include <nuttx/irq.h>
3535
#include <nuttx/arch.h>
36+
#include <nuttx/spinlock.h>
3637
#include <arch/board/board.h>
3738

3839
#include "arm_internal.h"
@@ -45,6 +46,8 @@
4546
****************************************************************************/
4647

4748
#ifdef CONFIG_DEBUG_GPIO_INFO
49+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
50+
4851
static const char g_portchar[4] =
4952
{
5053
'A', 'B', 'C', 'D'
@@ -529,7 +532,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
529532

530533
/* The following requires exclusive access to the GPIO registers */
531534

532-
flags = enter_critical_section();
535+
flags = spin_lock_irqsave(&g_configgpio_lock);
533536

534537
gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
535538
g_portchar[port], pinset, base, msg);
@@ -559,7 +562,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
559562
getreg32(base + SAM_GPIO_PARAMETER_OFFSET),
560563
getreg32(base + SAM_GPIO_VERSION_OFFSET));
561564

562-
leave_critical_section(flags);
565+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
563566
return OK;
564567
}
565568
#endif

‎arch/arm/src/sam34/sam_gpio.c

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333

3434
#include <nuttx/irq.h>
3535
#include <nuttx/arch.h>
36+
#include <nuttx/spinlock.h>
3637
#include <arch/board/board.h>
3738

3839
#include "arm_internal.h"
@@ -55,6 +56,8 @@
5556
* Private Data
5657
****************************************************************************/
5758

59+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
60+
5861
#ifdef CONFIG_DEBUG_GPIO_INFO
5962
static const char g_portchar[4] =
6063
{
@@ -476,7 +479,7 @@ int sam_configgpio(gpio_pinset_t cfgset)
476479

477480
/* Disable interrupts to prohibit re-entrance. */
478481

479-
flags = enter_critical_section();
482+
flags = spin_lock_irqsave(&g_configgpio_lock);
480483

481484
/* Enable writing to GPIO registers */
482485

@@ -511,7 +514,7 @@ int sam_configgpio(gpio_pinset_t cfgset)
511514
/* Disable writing to GPIO registers */
512515

513516
putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
514-
leave_critical_section(flags);
517+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
515518

516519
return ret;
517520
}
@@ -588,7 +591,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
588591

589592
/* The following requires exclusive access to the GPIO registers */
590593

591-
flags = enter_critical_section();
594+
flags = spin_lock_irqsave(&g_configgpio_lock);
592595

593596
gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
594597
g_portchar[port], pinset, base, msg);
@@ -646,7 +649,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
646649
#endif
647650
#endif
648651

649-
leave_critical_section(flags);
652+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
650653
return OK;
651654
}
652655
#endif

‎arch/arm/src/samv7/sam_gpio.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333

3434
#include <nuttx/irq.h>
3535
#include <nuttx/arch.h>
36+
#include <nuttx/spinlock.h>
3637
#include <arch/board/board.h>
3738

3839
#include "arm_internal.h"
@@ -75,6 +76,8 @@
7576
* Private Data
7677
****************************************************************************/
7778

79+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
80+
7881
#ifdef CONFIG_DEBUG_GPIO_INFO
7982
static const char g_portchar[SAMV7_NPIO] =
8083
{
@@ -497,7 +500,7 @@ int sam_configgpio(gpio_pinset_t cfgset)
497500

498501
/* Disable interrupts to prohibit re-entrance. */
499502

500-
flags = enter_critical_section();
503+
flags = spin_lock_irqsave(&g_configgpio_lock);
501504

502505
/* Enable writing to GPIO registers */
503506

@@ -606,7 +609,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
606609

607610
/* The following requires exclusive access to the GPIO registers */
608611

609-
flags = enter_critical_section();
612+
flags = spin_lock_irqsave(&g_configgpio_lock);
610613

611614
gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
612615
g_portchar[port], pinset, base, msg);

‎arch/arm/src/stm32/stm32_gpio.c

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333
#include <debug.h>
3434

3535
#include <nuttx/irq.h>
36+
#include <nuttx/spinlock.h>
3637

3738
#include "arm_internal.h"
3839
#include "chip.h"
@@ -43,6 +44,12 @@
4344
# pragma message "CONFIG_STM32_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py"
4445
#endif
4546

47+
/****************************************************************************
48+
* Private Data
49+
****************************************************************************/
50+
51+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
52+
4653
/****************************************************************************
4754
* Public Data
4855
****************************************************************************/
@@ -299,7 +306,7 @@ int stm32_configgpio(uint32_t cfgset)
299306
* exclusive access to all of the GPIO configuration registers.
300307
*/
301308

302-
flags = enter_critical_section();
309+
flags = spin_lock_irqsave(&g_configgpio_lock);
303310

304311
/* Decode the mode and configuration */
305312

@@ -339,7 +346,7 @@ int stm32_configgpio(uint32_t cfgset)
339346
{
340347
/* Its an alternate function pin... we can return early */
341348

342-
leave_critical_section(flags);
349+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
343350
return OK;
344351
}
345352
}
@@ -366,7 +373,7 @@ int stm32_configgpio(uint32_t cfgset)
366373
{
367374
/* Neither... we can return early */
368375

369-
leave_critical_section(flags);
376+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
370377
return OK;
371378
}
372379
}
@@ -393,7 +400,7 @@ int stm32_configgpio(uint32_t cfgset)
393400
regval |= (1 << pin);
394401
putreg32(regval, regaddr);
395402

396-
leave_critical_section(flags);
403+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
397404
return OK;
398405
}
399406
#endif
@@ -468,7 +475,7 @@ int stm32_configgpio(uint32_t cfgset)
468475
* exclusive access to all of the GPIO configuration registers.
469476
*/
470477

471-
flags = enter_critical_section();
478+
flags = spin_lock_irqsave(&g_configgpio_lock);
472479

473480
/* Determine the alternate function (Only alternate function pins) */
474481

@@ -684,7 +691,7 @@ int stm32_configgpio(uint32_t cfgset)
684691
putreg32(regval, regaddr);
685692
}
686693

687-
leave_critical_section(flags);
694+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
688695
return OK;
689696
}
690697
#endif

‎arch/arm/src/stm32f0l0g0/stm32_gpio.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434

3535
#include <arch/irq.h>
3636
#include <arch/stm32f0l0g0/chip.h>
37+
#include <nuttx/spinlock.h>
3738

3839
#include "arm_internal.h"
3940
#include "chip.h"
@@ -49,6 +50,12 @@
4950
# pragma message "CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP will be deprecated migrate board.h see tools/stm32_pinmap_tool.py"
5051
#endif
5152

53+
/****************************************************************************
54+
* Private Data
55+
****************************************************************************/
56+
57+
static spinlock_t g_configgpio_lock = SP_UNLOCKED;
58+
5259
/****************************************************************************
5360
* Public Data
5461
****************************************************************************/
@@ -178,7 +185,7 @@ int stm32_configgpio(uint32_t cfgset)
178185
* exclusive access to all of the GPIO configuration registers.
179186
*/
180187

181-
flags = enter_critical_section();
188+
flags = spin_lock_irqsave(&g_configgpio_lock);
182189

183190
/* Now apply the configuration to the mode register */
184191

@@ -339,7 +346,7 @@ int stm32_configgpio(uint32_t cfgset)
339346
#endif
340347
}
341348

342-
leave_critical_section(flags);
349+
spin_unlock_irqrestore(&g_configgpio_lock, flags);
343350
return OK;
344351
}
345352

0 commit comments

Comments
 (0)