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eren-terziogluxiaoxiang781216
eren-terzioglu
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arch/risc-v/esp32[c6]: Add LP_UART support
Add LP_UART support for esp32c6 Signed-off-by: Eren Terzioglu <[email protected]>
1 parent 880c8e5 commit 1c48c0c

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6 files changed

+338
-23
lines changed

6 files changed

+338
-23
lines changed

‎arch/risc-v/src/common/espressif/Kconfig

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,10 @@ config ESPRESSIF_UART
261261
bool
262262
default n
263263

264+
config ESPRESSIF_LP_UART
265+
bool
266+
default n
267+
264268
config ESPRESSIF_UART0
265269
bool "UART0"
266270
default y
@@ -275,6 +279,15 @@ config ESPRESSIF_UART1
275279
select UART1_SERIALDRIVER
276280
select ARCH_HAVE_SERIAL_TERMIOS
277281

282+
config ESPRESSIF_LP_UART0
283+
bool "LP UART0"
284+
default n
285+
depends on ARCH_CHIP_ESP32C6
286+
select ESPRESSIF_UART
287+
select ESPRESSIF_LP_UART
288+
select LPUART0_SERIALDRIVER
289+
select ARCH_HAVE_SERIAL_TERMIOS
290+
278291
config ESPRESSIF_TWAI
279292
bool "TWAI (CAN)"
280293
default n

‎arch/risc-v/src/common/espressif/esp_config.h

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,9 @@
4040
/* Are any UARTs enabled? */
4141

4242
#undef HAVE_UART_DEVICE
43-
#if defined(CONFIG_ESPRESSIF_UART0) || defined(CONFIG_ESPRESSIF_UART1)
43+
#if defined(CONFIG_ESPRESSIF_UART0) || \
44+
defined(CONFIG_ESPRESSIF_UART1) || \
45+
defined(CONFIG_ESPRESSIF_LP_UART0)
4446
# define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */
4547
#endif
4648

@@ -61,15 +63,23 @@
6163
#undef CONSOLE_UART
6264
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_UART0)
6365
# undef CONFIG_UART1_SERIAL_CONSOLE
66+
# undef CONFIG_LPUART0_SERIAL_CONSOLE
6467
# define HAVE_SERIAL_CONSOLE 1
6568
# define CONSOLE_UART 1
6669
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_UART1)
6770
# undef CONFIG_UART0_SERIAL_CONSOLE
71+
# undef CONFIG_LPUART0_SERIAL_CONSOLE
72+
# define HAVE_SERIAL_CONSOLE 1
73+
# define CONSOLE_UART 1
74+
#elif defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_LP_UART0)
75+
# undef CONFIG_UART0_SERIAL_CONSOLE
76+
# undef CONFIG_UART1_SERIAL_CONSOLE
6877
# define HAVE_SERIAL_CONSOLE 1
6978
# define CONSOLE_UART 1
7079
#else
7180
# undef CONFIG_UART0_SERIAL_CONSOLE
7281
# undef CONFIG_UART1_SERIAL_CONSOLE
82+
# undef CONFIG_LPUART0_SERIAL_CONSOLE
7383
#endif
7484

7585
#ifdef CONFIG_ESPRESSIF_USBSERIAL

‎arch/risc-v/src/common/espressif/esp_lowputc.c

Lines changed: 184 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,23 @@
5151
#include "hal/uart_hal.h"
5252
#include "periph_ctrl.h"
5353
#include "soc/gpio_sig_map.h"
54+
#ifdef CONFIG_ESPRESSIF_LP_UART
55+
# include "lp_core_uart.h"
56+
# include "soc/uart_pins.h"
57+
# include "hal/rtc_io_hal.h"
58+
# include "soc/uart_periph.h"
59+
#endif
60+
61+
/****************************************************************************
62+
* Pre-processor Definitions
63+
****************************************************************************/
64+
65+
#ifdef CONFIG_ESPRESSIF_LP_UART
66+
# define ESP_LP_UART0_ID LP_UART_NUM_0
67+
# define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
68+
#else
69+
# define ESP_LP_UART0_ID UART_NUM_MAX
70+
#endif /* CONFIG_ESPRESSIF_LP_UART */
5471

5572
/****************************************************************************
5673
* Private Types
@@ -110,6 +127,7 @@ struct esp_uart_s g_uart0_config =
110127
.rs485_dir_polarity = true,
111128
#endif
112129
#endif
130+
.clk_src = UART_SCLK_DEFAULT,
113131
.hal = &g_uart0_hal,
114132
.lock = SP_UNLOCKED
115133
};
@@ -164,13 +182,117 @@ struct esp_uart_s g_uart1_config =
164182
.rs485_dir_polarity = true,
165183
#endif
166184
#endif
185+
.clk_src = UART_SCLK_DEFAULT,
167186
.hal = &g_uart1_hal,
168187
.lock = SP_UNLOCKED
169188
};
170189

171190
#endif /* CONFIG_ESPRESSIF_UART1 */
191+
192+
#ifdef CONFIG_ESPRESSIF_LP_UART0
193+
194+
static uart_hal_context_t g_lp_uart0_hal =
195+
{
196+
.dev = (hal_uart_dev_t *)&LP_UART
197+
};
198+
199+
struct esp_uart_s g_lp_uart0_config =
200+
{
201+
.source = LP_UART_INTR_SOURCE,
202+
.cpuint = -ENOMEM,
203+
.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
204+
.id = ESP_LP_UART0_ID,
205+
.irq = ESP_IRQ_LP_UART,
206+
.baud = CONFIG_LPUART0_BAUD,
207+
.stop_b2 = CONFIG_LPUART0_2STOP,
208+
.bits = CONFIG_LPUART0_BITS,
209+
.parity = CONFIG_LPUART0_PARITY,
210+
.txpin = LP_UART_DEFAULT_TX_GPIO_NUM,
211+
.txsig = LP_U0TXD_MUX_FUNC,
212+
.rxpin = LP_UART_DEFAULT_RX_GPIO_NUM,
213+
.rxsig = LP_U0RXD_MUX_FUNC,
214+
#ifdef CONFIG_SERIAL_IFLOWCONTROL
215+
.rtspin = LP_UART_DEFAULT_RTS_GPIO_NUM,
216+
.rtssig = LP_U0RTS_MUX_FUNC,
217+
#ifdef CONFIG_LPUART0_IFLOWCONTROL
218+
.iflow = true, /* input flow control (RTS) enabled */
219+
#else
220+
.iflow = false, /* input flow control (RTS) disabled */
221+
#endif
222+
#endif
223+
#ifdef CONFIG_SERIAL_OFLOWCONTROL
224+
.ctspin = LP_UART_DEFAULT_CTS_GPIO_NUM,
225+
.ctssig = LP_U0CTS_MUX_FUNC,
226+
#ifdef CONFIG_LPUART0_OFLOWCONTROL
227+
.oflow = true, /* output flow control (CTS) enabled */
228+
#else
229+
.oflow = false, /* output flow control (CTS) disabled */
230+
#endif
231+
#endif
232+
.clk_src = LP_UART_SCLK_DEFAULT,
233+
.hal = &g_lp_uart0_hal,
234+
.lock = SP_UNLOCKED
235+
};
236+
237+
#endif /* CONFIG_ESPRESSIF_LP_UART0 */
238+
172239
#endif /* HAVE_UART_DEVICE */
173240

241+
/****************************************************************************
242+
* Private Functions
243+
****************************************************************************/
244+
245+
#ifdef CONFIG_ESPRESSIF_LP_UART
246+
/****************************************************************************
247+
* Name: esp_lowputc_lp_uart_config_io
248+
*
249+
* Description:
250+
* Configures LP UART pin.
251+
*
252+
* Parameters:
253+
* priv - Pointer to the private driver struct.
254+
* pin - Pin number to configure.
255+
* direction - Pin direction to configure.
256+
* idx - Pin idx to configure.
257+
*
258+
* Return Value:
259+
* None.
260+
*
261+
****************************************************************************/
262+
263+
static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
264+
int8_t pin,
265+
rtc_gpio_mode_t direction,
266+
uint32_t idx)
267+
{
268+
irqstate_t flags = spin_lock_irqsave(&priv->lock);
269+
int lp_pin = rtc_io_num_map[pin];
270+
271+
DEBUGASSERT(lp_pin != -1);
272+
273+
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
274+
RTCIO_RCC_ATOMIC()
275+
{
276+
rtcio_ll_enable_io_clock(true);
277+
}
278+
279+
#endif
280+
rtcio_hal_function_select(lp_pin, RTCIO_LL_FUNC_RTC);
281+
rtcio_hal_set_direction(pin, direction);
282+
283+
const uart_periph_sig_t *upin =
284+
&uart_periph_signal[LP_UART_NUM_0].pins[idx];
285+
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
286+
rtcio_hal_iomux_func_sel(lp_pin, upin->iomux_func);
287+
#else
288+
/* ToDo: Add LP UART for LP GPIO Matrix supported devices (e.g ESP32-P4) */
289+
#endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */
290+
291+
spin_unlock_irqrestore(&priv->lock, flags);
292+
}
293+
294+
#endif /* CONFIG_ESPRESSIF_LP_UART */
295+
174296
/****************************************************************************
175297
* Public Functions
176298
****************************************************************************/
@@ -206,7 +328,10 @@ void esp_lowputc_send_byte(const struct esp_uart_s *priv, char byte)
206328

207329
void esp_lowputc_enable_sysclk(const struct esp_uart_s *priv)
208330
{
209-
periph_module_enable(PERIPH_UART0_MODULE + priv->id);
331+
if (priv->id < ESP_LP_UART0_ID)
332+
{
333+
periph_module_enable(PERIPH_UART0_MODULE + priv->id);
334+
}
210335
}
211336

212337
/****************************************************************************
@@ -284,26 +409,28 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
284409
{
285410
/* Configure the pins */
286411

287-
esp_configgpio(priv->rxpin, INPUT | PULLUP);
288-
esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
412+
if (priv->id < ESP_LP_UART0_ID)
413+
{
414+
esp_configgpio(priv->rxpin, INPUT | PULLUP);
415+
esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
289416

290-
esp_configgpio(priv->txpin, OUTPUT);
291-
esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
417+
esp_configgpio(priv->txpin, OUTPUT);
418+
esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
292419

293420
#ifdef CONFIG_SERIAL_IFLOWCONTROL
294-
if (priv->iflow)
295-
{
296-
esp_configgpio(priv->rtspin, OUTPUT);
297-
esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
298-
}
421+
if (priv->iflow)
422+
{
423+
esp_configgpio(priv->rtspin, OUTPUT);
424+
esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
425+
}
299426

300427
#endif
301428
#ifdef CONFIG_SERIAL_OFLOWCONTROL
302-
if (priv->oflow)
303-
{
304-
esp_configgpio(priv->ctspin, INPUT | PULLUP);
305-
esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
306-
}
429+
if (priv->oflow)
430+
{
431+
esp_configgpio(priv->ctspin, INPUT | PULLUP);
432+
esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
433+
}
307434
#endif
308435

309436
#ifdef HAVE_RS485
@@ -314,6 +441,41 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
314441
esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
315442
}
316443
#endif
444+
}
445+
#ifdef CONFIG_ESPRESSIF_LP_UART
446+
else
447+
{
448+
esp_lowputc_lp_uart_config_io(priv,
449+
priv->rxpin,
450+
RTC_GPIO_MODE_INPUT_ONLY,
451+
SOC_UART_RX_PIN_IDX);
452+
453+
esp_lowputc_lp_uart_config_io(priv,
454+
priv->txpin,
455+
RTC_GPIO_MODE_OUTPUT_ONLY,
456+
SOC_UART_TX_PIN_IDX);
457+
458+
#ifdef CONFIG_SERIAL_IFLOWCONTROL
459+
if (priv->iflow)
460+
{
461+
esp_lowputc_lp_uart_config_io(priv,
462+
priv->rtspin,
463+
RTC_GPIO_MODE_OUTPUT_ONLY,
464+
SOC_UART_RTS_PIN_IDX);
465+
}
466+
#endif
467+
468+
#ifdef CONFIG_SERIAL_OFLOWCONTROL
469+
if (priv->oflow)
470+
{
471+
esp_lowputc_lp_uart_config_io(priv,
472+
priv->ctspin,
473+
RTC_GPIO_MODE_INPUT_ONLY,
474+
SOC_UART_CTS_PIN_IDX);
475+
}
476+
#endif
477+
}
478+
#endif /* CONFIG_ESPRESSIF_LP_UART */
317479
}
318480

319481
/****************************************************************************
@@ -357,6 +519,8 @@ void riscv_lowputc(char ch)
357519
struct esp_uart_s *priv = &g_uart0_config;
358520
# elif defined (CONFIG_UART1_SERIAL_CONSOLE)
359521
struct esp_uart_s *priv = &g_uart1_config;
522+
# elif defined (CONFIG_LPUART0_SERIAL_CONSOLE)
523+
struct esp_uart_s *priv = &g_lp_uart0_config;
360524
# endif
361525

362526
/* Wait until the TX FIFO has space to insert new char */
@@ -393,5 +557,10 @@ void esp_lowsetup(void)
393557
esp_lowputc_config_pins(&g_uart1_config);
394558
#endif
395559

560+
#ifdef CONFIG_ESPRESSIF_LP_UART0
561+
esp_lowputc_enable_sysclk(&g_lp_uart0_config);
562+
esp_lowputc_config_pins(&g_lp_uart0_config);
563+
#endif
564+
396565
#endif /* !CONFIG_SUPPRESS_UART_CONFIG */
397566
}

‎arch/risc-v/src/common/espressif/esp_lowputc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,14 @@ struct esp_uart_s
8080
uint8_t rs485_dir_gpio; /* UART RS-485 DIR GPIO pin cfg */
8181
bool rs485_dir_polarity; /* UART RS-485 DIR TXEN polarity */
8282
#endif
83+
soc_module_clk_t clk_src; /* Clock source */
8384
uart_hal_context_t *hal; /* HAL context */
8485
spinlock_t lock; /* Spinlock */
8586
};
8687

8788
extern struct esp_uart_s g_uart0_config;
8889
extern struct esp_uart_s g_uart1_config;
90+
extern struct esp_uart_s g_lp_uart0_config;
8991

9092
/****************************************************************************
9193
* Public Function Prototypes

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