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#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
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#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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- #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (? ?) */
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- #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (? ?) */
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+ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (/?/ ?) */
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+ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (/?/ ?) */
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#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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- #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (? ?) */
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- #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (? ?) */
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- #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (? ?) */
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- #define PCI_PM_DATA_REGISTER 7 /* (? ?) */
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+ #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (/?/ ?) */
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+ #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (/?/ ?) */
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+ #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (/?/ ?) */
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+ #define PCI_PM_DATA_REGISTER 7 /* (/?/ ?) */
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#define PCI_PM_SIZEOF 8
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/* AGP registers */
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