esp32: fix initialization with PSRAM + SMP

Cache flush must be done prior to the APP cpu initalization. This,
however, must be true for the case where PSRAM is not available or
not selected. To do that, this commit flushs the cache during the
device initialization.

Author: tmedicci

arch/xtensa/src/common/espressif/esp_loader.c

@@ -273,8 +273,12 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
 #endif
 
 #ifdef CONFIG_ARCH_CHIP_ESP32
-  cache_read_disable(0);
-  cache_flush(0);
+  cache_read_disable(PRO_CPU_NUM);
+  cache_flush(PRO_CPU_NUM);
+#  ifdef CONFIG_SMP
+  cache_flush(APP_CPU_NUM);
+  cache_read_enable(APP_CPU_NUM);
+#  endif
 #else
   cache_hal_disable(CACHE_TYPE_ALL);
 #endif

arch/xtensa/src/esp32/esp32_spiram.c

@@ -68,13 +68,6 @@
 #  error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
 #endif
 
-/****************************************************************************
- * ROM Function Prototypes
- ****************************************************************************/
-
-extern void cache_flush(int cpu);
-extern void cache_read_enable(int cpu);
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -253,8 +246,6 @@ void IRAM_ATTR esp_spiram_init_cache(void)
   /* Flush and enable icache for APP CPU */
 
 #ifdef CONFIG_SMP
-  cache_flush(APP_CPU_NUM);
-  cache_read_enable(APP_CPU_NUM);
   regval  = getreg32(DPORT_APP_CACHE_CTRL1_REG);
   regval &= ~(1 << DPORT_APP_CACHE_MASK_DRAM1);
   putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);