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raiden00plxiaoxiang781216
raiden00pl
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xiaoxiang781216
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arch/arm/stm32/stm32_dumpgpio.c: fix print warnings
fix print warnings for stm32_dumpgpio.c
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‎arch/arm/src/stm32/stm32_dumpgpio.c

Lines changed: 31 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -107,18 +107,20 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
107107
flags = enter_critical_section();
108108

109109
#if defined(CONFIG_STM32_STM32F10XX)
110-
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
110+
_info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n",
111111
g_portchar[port], pinset, base, msg);
112112

113113
if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
114114
{
115-
_info(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
115+
_info(" CR: %08" PRIx32 " %08" PRIx32 " IDR: %04" PRIx32
116+
" ODR: %04" PRIx32 " LCKR: %04" PRIx32 "\n",
116117
getreg32(base + STM32_GPIO_CRH_OFFSET),
117118
getreg32(base + STM32_GPIO_CRL_OFFSET),
118119
getreg32(base + STM32_GPIO_IDR_OFFSET),
119120
getreg32(base + STM32_GPIO_ODR_OFFSET),
120121
getreg32(base + STM32_GPIO_LCKR_OFFSET));
121-
_info(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
122+
_info(" EVCR: %02" PRIx32 " MAPR: %08" PRIx32 " CR: %04" PRIx32
123+
" %04" PRIx32 " %04" PRIx32 " %04" PRIx32 "\n",
122124
getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
123125
getreg32(STM32_AFIO_EXTICR1),
124126
getreg32(STM32_AFIO_EXTICR2),
@@ -139,69 +141,75 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
139141

140142
if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
141143
{
142-
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
144+
_info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32
145+
" OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n",
143146
getreg32(base + STM32_GPIO_MODER_OFFSET),
144147
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
145148
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
146149
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
147-
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
150+
_info(" IDR: %04" PRIx32 " ODR: %04" PRIx32
151+
" BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n",
148152
getreg32(base + STM32_GPIO_IDR_OFFSET),
149153
getreg32(base + STM32_GPIO_ODR_OFFSET),
150154
getreg32(base + STM32_GPIO_BSRR_OFFSET),
151155
getreg32(base + STM32_GPIO_LCKR_OFFSET));
152-
_info(" AFRH: %08x AFRL: %08x\n",
156+
_info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n",
153157
getreg32(base + STM32_GPIO_AFRH_OFFSET),
154158
getreg32(base + STM32_GPIO_AFRL_OFFSET));
155159
}
156160
else
157161
{
158-
_info(" GPIO%c not enabled: AHBENR: %08x\n",
162+
_info(" GPIO%c not enabled: AHBENR: %08" PRIx32 "\n",
159163
g_portchar[port], getreg32(STM32_RCC_AHBENR));
160164
}
161165

162166
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
163167
defined(CONFIG_STM32_STM32F33XX)
164168
DEBUGASSERT(port < STM32_NGPIO_PORTS);
165169

166-
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
170+
_info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n",
167171
g_portchar[port], pinset, base, msg);
168172

169173
/* GPIOs are always enabled */
170174

171-
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
175+
_info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32
176+
" OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n",
172177
getreg32(base + STM32_GPIO_MODER_OFFSET),
173178
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
174179
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
175180
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
176-
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
181+
_info(" IDR: %04" PRIx32 " ODR: %04" PRIx32
182+
" BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n",
177183
getreg32(base + STM32_GPIO_IDR_OFFSET),
178184
getreg32(base + STM32_GPIO_ODR_OFFSET),
179185
getreg32(base + STM32_GPIO_BSRR_OFFSET),
180186
getreg32(base + STM32_GPIO_LCKR_OFFSET));
181-
_info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
187+
_info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 " BRR: %04" PRIx32 "\n",
182188
getreg32(base + STM32_GPIO_AFRH_OFFSET),
183189
getreg32(base + STM32_GPIO_AFRL_OFFSET),
184190
getreg32(base + STM32_GPIO_BRR_OFFSET));
185191

186192
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
187193
DEBUGASSERT(port < STM32_NGPIO_PORTS);
188194

189-
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
195+
_info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n",
190196
g_portchar[port], pinset, base, msg);
191197

192198
if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
193199
{
194-
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
200+
_info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32
201+
" OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n",
195202
getreg32(base + STM32_GPIO_MODER_OFFSET),
196203
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
197204
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
198205
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
199-
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
206+
_info(" IDR: %04" PRIx32 " ODR: %04" PRIx32
207+
" BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n",
200208
getreg32(base + STM32_GPIO_IDR_OFFSET),
201209
getreg32(base + STM32_GPIO_ODR_OFFSET),
202210
getreg32(base + STM32_GPIO_BSRR_OFFSET),
203211
getreg32(base + STM32_GPIO_LCKR_OFFSET));
204-
_info(" AFRH: %08x AFRL: %08x\n",
212+
_info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n",
205213
getreg32(base + STM32_GPIO_AFRH_OFFSET),
206214
getreg32(base + STM32_GPIO_AFRL_OFFSET));
207215
}
@@ -214,29 +222,32 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
214222
#elif defined(CONFIG_STM32_STM32G4XXX)
215223
DEBUGASSERT(port < STM32_NGPIO_PORTS);
216224

217-
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
225+
_info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n",
218226
g_portchar[port], pinset, base, msg);
219227

220228
if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
221229
{
222-
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
230+
_info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32
231+
" OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n",
223232
getreg32(base + STM32_GPIO_MODER_OFFSET),
224233
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
225234
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
226235
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
227-
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
236+
_info(" IDR: %04" PRIx32 " ODR: %04" PRIx32
237+
" BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n",
228238
getreg32(base + STM32_GPIO_IDR_OFFSET),
229239
getreg32(base + STM32_GPIO_ODR_OFFSET),
230240
getreg32(base + STM32_GPIO_BSRR_OFFSET),
231241
getreg32(base + STM32_GPIO_LCKR_OFFSET));
232-
_info(" AFRH: %08x AFRL: %08x BRR: %04x\n",
242+
_info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32
243+
" BRR: %04" PRIx32 "\n",
233244
getreg32(base + STM32_GPIO_AFRH_OFFSET),
234245
getreg32(base + STM32_GPIO_AFRL_OFFSET),
235246
getreg32(base + STM32_GPIO_BRR_OFFSET));
236247
}
237248
else
238249
{
239-
_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
250+
_info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n",
240251
g_portchar[port], getreg32(STM32_RCC_AHB2ENR));
241252
}
242253

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