|
47 | 47 | * riscv_dispatch_irq
|
48 | 48 | ****************************************************************************/
|
49 | 49 |
|
| 50 | +#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP |
50 | 51 | void *riscv_dispatch_irq(uintptr_t vector, uintreg_t *regs)
|
51 | 52 | {
|
52 |
| -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP |
53 | 53 | int irq = (vector & 0x3f);
|
| 54 | + DEBUGASSERT(irq <= RISCV_IRQ_EXT); |
54 | 55 |
|
55 | 56 | if ((vector & RISCV_IRQ_BIT) != 0)
|
56 | 57 | {
|
57 | 58 | irq += RISCV_IRQ_ASYNC;
|
58 | 59 | }
|
59 | 60 |
|
60 |
| - /* Firstly, check if the irq is machine external interrupt */ |
61 |
| - |
62 |
| - if (irq == RISCV_IRQ_EXT) |
| 61 | + if (irq < RISCV_IRQ_EXT) |
63 | 62 | {
|
64 |
| - uint32_t ext = getreg32(LITEX_PLIC_CLAIM); |
65 |
| - |
66 |
| - /* Add the value to nuttx irq which is offset to the ext */ |
67 |
| - |
68 |
| - irq = RISCV_IRQ_EXT + ext; |
69 |
| - } |
70 |
| - |
71 |
| - /* Acknowledge the interrupt */ |
72 |
| - |
73 |
| - riscv_ack_irq(irq); |
74 |
| - |
75 |
| - /* EXT means no interrupt */ |
76 |
| - |
77 |
| - if (irq != RISCV_IRQ_EXT) |
78 |
| - { |
79 |
| - /* Deliver the IRQ */ |
80 |
| - |
81 | 63 | regs = riscv_doirq(irq, regs);
|
82 | 64 | }
|
83 |
| - |
84 |
| - if (irq > RISCV_IRQ_EXT) |
| 65 | + else |
85 | 66 | {
|
86 |
| - /* Then write PLIC_CLAIM to clear pending in PLIC */ |
87 |
| - |
88 |
| - putreg32(irq - RISCV_IRQ_EXT, LITEX_PLIC_CLAIM); |
| 67 | + uint32_t ext = getreg32(LITEX_PLIC_CLAIM); |
| 68 | + do |
| 69 | + { |
| 70 | + regs = riscv_doirq(RISCV_IRQ_EXT + ext, regs); |
| 71 | + putreg32(ext, LITEX_PLIC_CLAIM); |
| 72 | + ext = getreg32(LITEX_PLIC_CLAIM); |
| 73 | + } |
| 74 | + while (ext); |
89 | 75 | }
|
90 | 76 |
|
91 |
| -#else |
| 77 | + return regs; |
| 78 | +} |
| 79 | +#else |
| 80 | +void *riscv_dispatch_irq(uintptr_t vector, uintreg_t *regs) |
| 81 | +{ |
92 | 82 | int i;
|
93 | 83 | int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
|
94 | 84 |
|
@@ -127,6 +117,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintreg_t *regs)
|
127 | 117 |
|
128 | 118 | regs = riscv_doirq(irq, regs);
|
129 | 119 |
|
130 |
| -#endif /* CONFIG_LITEX_CORE_VEXRISCV_SMP */ |
131 | 120 | return regs;
|
132 | 121 | }
|
| 122 | +#endif |
0 commit comments