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yangshuyongxiaoxiang781216
yangshuyong
authored and
xiaoxiang781216
committed
Changed the x86 64 pci driver
Signed-off-by: yangshuyong <[email protected]> Signed-off-by: lipengfei28 <[email protected]>
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+209
-77
lines changed

3 files changed

+209
-77
lines changed

‎arch/x86_64/src/common/x86_64_pci.c

Lines changed: 151 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -35,175 +35,250 @@
3535
* Pre-processor Definitions
3636
****************************************************************************/
3737

38-
#define PCI_CFG_ADDR 0xcf8
39-
#define PCI_DATA_ADDR 0xcfc
40-
#define PCI_CFG_EN (1 << 31)
38+
#define PCI_CFG_ADDR 0xcf8
39+
#define PCI_DATA_ADDR 0xcfc
40+
#define PCI_CFG_EN (1 << 31)
4141

4242
/****************************************************************************
4343
* Private Functions Definitions
4444
****************************************************************************/
4545

46-
static void x86_64_pci_cfg_write(struct pci_dev_s *dev, int reg,
47-
uint32_t val, int width);
48-
static uint32_t x86_64_pci_cfg_read(struct pci_dev_s *dev, int reg,
49-
int width);
50-
static int x86_64_pci_map_bar(uint64_t addr, uint64_t len);
51-
static uint32_t x86_64_pci_io_read(const volatile void *addr, int width);
52-
static void x86_64_pci_io_write(const volatile void *addr, uint32_t val,
53-
int width);
46+
static int x86_64_pci_write(struct pci_bus_s *bus, unsigned int devfn,
47+
int where, int size, uint32_t val);
48+
static int x86_64_pci_read(struct pci_bus_s *bus, unsigned int devfn,
49+
int where, int size, uint32_t *val);
50+
static uintptr_t x86_64_pci_map(struct pci_bus_s *bus, uintptr_t start,
51+
uintptr_t end);
52+
static int x86_64_pci_read_io(struct pci_bus_s *bus, uintptr_t addr,
53+
int size, uint32_t *val);
54+
static int x86_64_pci_write_io(struct pci_bus_s *bus, uintptr_t addr,
55+
int size, uint32_t val);
5456

5557
/****************************************************************************
5658
* Private Data
5759
****************************************************************************/
5860

59-
static const struct pci_bus_ops_s g_x86_64_pci_bus_ops =
61+
static const struct pci_ops_s g_x86_64_pci_ops =
6062
{
61-
.pci_cfg_write = x86_64_pci_cfg_write,
62-
.pci_cfg_read = x86_64_pci_cfg_read,
63-
.pci_map_bar = x86_64_pci_map_bar,
64-
.pci_io_read = x86_64_pci_io_read,
65-
.pci_io_write = x86_64_pci_io_write,
63+
.write = x86_64_pci_write,
64+
.read = x86_64_pci_read,
65+
.map = x86_64_pci_map,
66+
.read_io = x86_64_pci_read_io,
67+
.write_io = x86_64_pci_write_io,
6668
};
6769

68-
static struct pci_bus_s g_x86_64_pci_bus =
70+
static struct pci_controller_s g_x86_64_pci =
6971
{
70-
.ops = &g_x86_64_pci_bus_ops,
72+
.ops = &g_x86_64_pci_ops
7173
};
7274

7375
/****************************************************************************
7476
* Private Functions
7577
****************************************************************************/
7678

7779
/****************************************************************************
78-
* Name: x86_64_pci_cfg_write
80+
* Name: x86_64_pci_write
7981
*
8082
* Description:
81-
* Write 8, 16, 32, 64 bits data to PCI-E configuration space of device
83+
* Write 8, 16, 32, 64 bits data to PCI configuration space of device
8284
* specified by dev
8385
*
8486
* Input Parameters:
85-
* bdf - Device private data
86-
* reg - A pointer to the read-only buffer of data to be written
87-
* size - The number of bytes to send from the buffer
87+
* bus - Bus that PCI device resides
88+
* devfn - The device and function bit field of bdf
89+
* where - Offset in the specify PCI device cfg address space
90+
* size - The number of bytes to send from the buffer
91+
* val - The value to write
8892
*
8993
* Returned Value:
9094
* 0: success, <0: A negated errno
9195
*
9296
****************************************************************************/
9397

94-
static void x86_64_pci_cfg_write(struct pci_dev_s *dev, int reg,
95-
uint32_t val, int width)
98+
static int x86_64_pci_write(struct pci_bus_s *bus, unsigned int devfn,
99+
int where, int size, uint32_t val)
96100
{
97-
uint8_t offset_mask = (4 - width);
101+
uint8_t offset_mask = (4 - size);
98102

99-
outl(PCI_CFG_EN | (dev->bdf << 8) | reg, PCI_CFG_ADDR);
100-
switch (width)
103+
outl(PCI_CFG_EN | (bus->number << 16) | (devfn << 8) | where,
104+
PCI_CFG_ADDR);
105+
106+
switch (size)
101107
{
102108
case 1:
103-
outb(val, PCI_DATA_ADDR + (reg & offset_mask));
104-
return;
109+
outb(val, PCI_DATA_ADDR + (where & offset_mask));
110+
break;
105111
case 2:
106-
outw(val, PCI_DATA_ADDR + (reg & offset_mask));
107-
return;
112+
outw(val, PCI_DATA_ADDR + (where & offset_mask));
113+
break;
108114
case 4:
109115
outl(val, PCI_DATA_ADDR);
110-
return;
116+
break;
111117
default:
112-
pcierr("Invalid cfg write width %d\n", width);
118+
pcierr("Invalid cfg write size %d\n", size);
119+
return -EINVAL;
113120
}
121+
122+
return 0;
114123
}
115124

116125
/****************************************************************************
117-
* Name: x86_64_pci_cfg_read
126+
* Name: x86_64_pci_read
118127
*
119128
* Description:
120-
* Read 8, 16, 32, 64 bits data from PCI-E configuration space of device
129+
* Read 8, 16, 32, 64 bits data from PCI configuration space of device
121130
* specified by dev
122131
*
123132
* Input Parameters:
124-
* dev - Device private data
125-
* buffer - A pointer to a buffer to receive the data from the device
133+
* bus - Bus that PCI device resides
134+
* devfn - The device and function bit field of bdf
135+
* where - Offset in the specify PCI device cfg address space
126136
* size - The requested number of bytes to be read
137+
* val - A pointer to a buffer to receive the data from the device
127138
*
128139
* Returned Value:
129140
* 0: success, <0: A negated errno
130141
*
131142
****************************************************************************/
132143

133-
static uint32_t x86_64_pci_cfg_read(struct pci_dev_s *dev, int reg,
134-
int width)
144+
static int x86_64_pci_read(struct pci_bus_s *bus, unsigned int devfn,
145+
int where, int size, uint32_t *val)
135146
{
136-
uint32_t ret;
137-
uint8_t offset_mask = 4 - width;
147+
uint8_t offset_mask = 4 - size;
138148

139-
outl(PCI_CFG_EN | (dev->bdf << 8) | reg, PCI_CFG_ADDR);
149+
outl(PCI_CFG_EN | (bus->number << 16) | (devfn << 8) | where,
150+
PCI_CFG_ADDR);
140151

141-
switch (width)
152+
switch (size)
142153
{
143154
case 1:
144-
ret = inb(PCI_DATA_ADDR + (reg & offset_mask));
145-
return ret;
146-
155+
*val = inb(PCI_DATA_ADDR + (where & offset_mask));
156+
break;
147157
case 2:
148-
ret = inw(PCI_DATA_ADDR + (reg & offset_mask));
149-
return ret;
158+
*val = inw(PCI_DATA_ADDR + (where & offset_mask));
159+
break;
150160
case 4:
151-
ret = inl(PCI_DATA_ADDR);
152-
return ret;
161+
*val = inl(PCI_DATA_ADDR);
162+
break;
153163
default:
154-
pcierr("Invalid cfg read width %d\n", width);
164+
*val = 0;
165+
pcierr("Invalid cfg read size %d\n", size);
166+
return -EINVAL;
155167
}
156168

157-
return 0;
169+
return OK;
158170
}
159171

160-
static uint32_t x86_64_pci_io_read(const volatile void *addr, int width)
172+
/****************************************************************************
173+
* Name: x86_64_pci_read_io
174+
*
175+
* Description:
176+
* Read 8, 16, 32, 64 bits data from PCI io address space of x86 64 device
177+
*
178+
* Input Parameters:
179+
* bus - Bus that PCI device resides
180+
* addr - The address to received data
181+
* size - The requested number of bytes to be read
182+
* val - A pointer to a buffer to receive the data from the device
183+
*
184+
* Returned Value:
185+
* 0: success, <0: A negated errno
186+
*
187+
****************************************************************************/
188+
189+
static int x86_64_pci_read_io(struct pci_bus_s *bus, uintptr_t addr,
190+
int size, uint32_t *val)
161191
{
162-
uint16_t portaddr = (uint16_t)(intptr_t)addr;
192+
uint16_t portaddr = (uint16_t)addr;
163193

164-
switch (width)
194+
switch (size)
165195
{
166196
case 1:
167-
return (uint32_t)inb(portaddr);
197+
*val = (uint32_t)inb(portaddr);
198+
break;
168199
case 2:
169-
return (uint32_t)inw(portaddr);
200+
*val = (uint32_t)inw(portaddr);
201+
break;
170202
case 4:
171-
return (uint32_t)inl(portaddr);
203+
*val = (uint32_t)inl(portaddr);
204+
break;
172205
default:
173-
pcierr("Invalid read width %d\n", width);
206+
*val = 0;
207+
pcierr("Invalid read size %d\n", size);
174208
DEBUGPANIC();
209+
return -EINVAL;
175210
}
176211

177-
return 0;
212+
return OK;
178213
}
179214

180-
static void x86_64_pci_io_write(const volatile void *addr, uint32_t val,
181-
int width)
215+
/****************************************************************************
216+
* Name: x86_64_pci_write_io
217+
*
218+
* Description:
219+
* Write 8, 16, 32, 64 bits data to PCI io address space of x86 64 device
220+
*
221+
* Input Parameters:
222+
* bus - Bus that PCI device resides
223+
* addr - The address to write data
224+
* size - The requested number of bytes to be write
225+
* val - The value to write
226+
*
227+
* Returned Value:
228+
* 0: success, <0: A negated errno
229+
*
230+
****************************************************************************/
231+
232+
static int x86_64_pci_write_io(struct pci_bus_s *bus, uintptr_t addr,
233+
int size, uint32_t val)
182234
{
183-
uint16_t portaddr = (uint16_t)(intptr_t)addr;
235+
uint16_t portaddr = (uint16_t)addr;
184236

185-
switch (width)
237+
switch (size)
186238
{
187239
case 1:
188240
outb((uint8_t)val, portaddr);
189-
return;
241+
break;
190242
case 2:
191243
outw((uint16_t)val, portaddr);
192-
return;
244+
break;
193245
case 4:
194246
outl((uint32_t)val, portaddr);
195-
return;
247+
break;
196248
default:
197-
pcierr("Invalid write width %d\n", width);
249+
pcierr("Invalid write size %d\n", size);
198250
DEBUGPANIC();
251+
return -EINVAL;
199252
}
253+
254+
return OK;
200255
}
201256

202-
static int x86_64_pci_map_bar(uint64_t addr, uint64_t len)
257+
/****************************************************************************
258+
* Name: x86_64_pci_map
259+
*
260+
* Description:
261+
* Map a memory region
262+
*
263+
* Input Parameters:
264+
* bus - Bus that PCI device resides
265+
* start - The start address to map
266+
* end - The end address to map
267+
*
268+
* Returned Value:
269+
* >0: success, 0: A positive value errno
270+
*
271+
****************************************************************************/
272+
273+
static uintptr_t x86_64_pci_map(struct pci_bus_s *bus, uintptr_t start,
274+
uintptr_t end)
203275
{
204-
up_map_region((void *)(uintptr_t)addr, len,
205-
X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_NOCACHE | X86_PAGE_GLOBAL);
206-
return OK;
276+
int ret;
277+
278+
ret = up_map_region((void *)start, end - start + 1, X86_PAGE_WR |
279+
X86_PAGE_PRESENT | X86_PAGE_NOCACHE | X86_PAGE_GLOBAL);
280+
281+
return ret < 0 ? 0 : start;
207282
}
208283

209284
/****************************************************************************
@@ -214,12 +289,11 @@ static int x86_64_pci_map_bar(uint64_t addr, uint64_t len)
214289
* Name: x86_64_pci_init
215290
*
216291
* Description:
217-
* Initialize the PCI-E bus
292+
* Initialize the PCI bus
218293
*
219294
****************************************************************************/
220295

221296
void x86_64_pci_init(void)
222297
{
223-
pciinfo("Initializing PCI Bus\n");
224-
pci_initialize(&g_x86_64_pci_bus);
298+
pci_register_controller(&g_x86_64_pci);
225299
}

‎drivers/pci/pci.c

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,36 @@
7474
return ret; \
7575
}
7676

77+
#define PCI_BUS_READ_IO(len, type, size) \
78+
int pci_bus_read_io_##len(FAR struct pci_bus_s *bus, uintptr_t where, \
79+
FAR type *value) \
80+
{ \
81+
int ret = -EINVAL; \
82+
uint32_t data = 0; \
83+
\
84+
if (!PCI_##len##_BAD) \
85+
{ \
86+
ret = bus->ctrl->ops->read_io(bus, where, size, &data); \
87+
} \
88+
\
89+
*value = (type)data; \
90+
return ret; \
91+
}
92+
93+
#define PCI_BUS_WRITE_IO(len, type, size) \
94+
int pci_bus_write_io_##len(FAR struct pci_bus_s *bus, uintptr_t where, \
95+
type value) \
96+
{ \
97+
int ret = -EINVAL; \
98+
\
99+
if (!PCI_##len##_BAD) \
100+
{ \
101+
ret = bus->ctrl->ops->write_io(bus, where, size, value); \
102+
} \
103+
\
104+
return ret; \
105+
}
106+
77107
#define pci_match_one_device(id, dev) \
78108
(((id)->vendor == PCI_ANY_ID || (id)->vendor == (dev)->vendor) && \
79109
((id)->device == PCI_ANY_ID || (id)->device == (dev)->device) && \
@@ -1171,3 +1201,9 @@ PCI_BUS_READ_CONFIG(dword, uint32_t, 4)
11711201
PCI_BUS_WRITE_CONFIG(byte, uint8_t, 1)
11721202
PCI_BUS_WRITE_CONFIG(word, uint16_t, 2)
11731203
PCI_BUS_WRITE_CONFIG(dword, uint32_t, 4)
1204+
PCI_BUS_READ_IO(byte, uint8_t, 1)
1205+
PCI_BUS_READ_IO(word, uint16_t, 2)
1206+
PCI_BUS_READ_IO(dword, uint32_t, 4)
1207+
PCI_BUS_WRITE_IO(byte, uint8_t, 1)
1208+
PCI_BUS_WRITE_IO(word, uint16_t, 2)
1209+
PCI_BUS_WRITE_IO(dword, uint32_t, 4)

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