riscv_cpustart.c: Fix reading of interrupt status

pussuw · xiaoxiang781216 · commit 8811eee0f4e6 · 2024-10-17T18:08:10.000+08:00
Let's read the interrupt status correctly, by checking for the interrupt
source bit instead of assuming no other status bit is set.
diff --git a/arch/risc-v/src/common/riscv_cpustart.c b/arch/risc-v/src/common/riscv_cpustart.c
@@ -81,7 +81,7 @@ void riscv_cpu_boot(int cpu)
     {
       asm("WFI");
     }
-  while (READ_CSR(CSR_IP) != IP_SIP);
+  while (!(READ_CSR(CSR_IP) & IP_SIP));
 
 #ifdef CONFIG_RISCV_PERCPU_SCRATCH
   /* Initialize the per CPU areas */

Original file line number	Diff line number	Diff line change
`@@ -81,7 +81,7 @@ void riscv_cpu_boot(int cpu)`
`81`	`81`	`{`
`82`	`82`	`asm("WFI");`
`83`	`83`	`}`
`84`		`- while (READ_CSR(CSR_IP) != IP_SIP);`
	`84`	`+ while (!(READ_CSR(CSR_IP) & IP_SIP));`
`85`	`85`
`86`	`86`	`#ifdef CONFIG_RISCV_PERCPU_SCRATCH`
`87`	`87`	`/* Initialize the per CPU areas */`