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178 | 178 | /* Define the Valid Configuration the G4 */
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179 | 179 |
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180 | 180 | # elif defined(CONFIG_STM32_STM32G4XXX)
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181 |
| -# if defined(CONFIG_STM32_FLASH_CONFIG_B) |
182 |
| -# define STM32_FLASH_NPAGES 32 |
183 |
| -# define STM32_FLASH_PAGESIZE 4096 |
184 |
| - |
185 |
| -# elif defined(CONFIG_STM32_FLASH_CONFIG_C) |
186 |
| -# define STM32_FLASH_NPAGES 64 |
187 |
| -# define STM32_FLASH_PAGESIZE 4096 |
188 |
| - |
189 |
| -# elif defined(CONFIG_STM32_FLASH_CONFIG_E) |
190 |
| -# define STM32_FLASH_NPAGES 128 |
191 |
| -# define STM32_FLASH_PAGESIZE 4096 |
| 181 | +# if defined(CONFIG_STM32_STM32G43XX) |
| 182 | +# if defined(CONFIG_STM32_FLASH_CONFIG_6) |
| 183 | +# define STM32_FLASH_NPAGES 16 |
| 184 | +# define STM32_FLASH_PAGESIZE 2048 |
| 185 | + |
| 186 | +# elif defined(CONFIG_STM32_FLASH_CONFIG_8) |
| 187 | +# define STM32_FLASH_NPAGES 32 |
| 188 | +# define STM32_FLASH_PAGESIZE 2048 |
| 189 | + |
| 190 | +# elif defined(CONFIG_STM32_FLASH_CONFIG_B) |
| 191 | +# define STM32_FLASH_NPAGES 64 |
| 192 | +# define STM32_FLASH_PAGESIZE 2048 |
| 193 | +# endif |
| 194 | +# elif defined(CONFIG_STM32_STM32G47XX) || defined(CONFIG_STM32_STM32G48XX) |
| 195 | +# if defined(CONFIG_STM32_FLASH_CONFIG_B) |
| 196 | +# define STM32_FLASH_SIZE 32 * 4096 |
| 197 | + |
| 198 | +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) |
| 199 | +# define STM32_FLASH_SIZE 64 * 4096 |
| 200 | + |
| 201 | +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) |
| 202 | +# define STM32_FLASH_SIZE 128 * 4096 |
| 203 | +# endif |
| 204 | +# elif defined(CONFIG_STM32_STM32G49XX) |
| 205 | +# elif defined(CONFIG_STM32_FLASH_CONFIG_C) |
| 206 | +# define STM32_FLASH_NPAGES 128 |
| 207 | +# define STM32_FLASH_PAGESIZE 2048 |
| 208 | + |
| 209 | +# elif defined(CONFIG_STM32_FLASH_CONFIG_E) |
| 210 | +# define STM32_FLASH_NPAGES 256 |
| 211 | +# define STM32_FLASH_PAGESIZE 2048 |
192 | 212 | # endif
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193 | 213 |
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194 | 214 | /* Define the Valid Configuration the F1 and F3 */
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261 | 281 | #elif defined(CONFIG_STM32_STM32G4XXX)
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262 | 282 | # define STM32_FLASH_PDKEYR_OFFSET 0x0004
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263 | 283 | # define STM32_FLASH_KEYR_OFFSET 0x0008
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264 |
| -# define STM32_FLASH_OPT_KEYR_OFFSET 0x000c |
| 284 | +# define STM32_FLASH_OPTKEYR_OFFSET 0x000c |
265 | 285 | # define STM32_FLASH_SR_OFFSET 0x0010
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266 | 286 | # define STM32_FLASH_CR_OFFSET 0x0014
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267 | 287 | # define STM32_FLASH_ECCR_OFFSET 0x0018
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324 | 344 | #elif defined(CONFIG_STM32_STM32G4XXX)
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325 | 345 | # define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET)
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326 | 346 | # define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
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327 |
| -# define STM32_FLASH_OPT_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPT_KEYR_OFFSET) |
| 347 | +# define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) |
328 | 348 | # define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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329 | 349 | # define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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330 | 350 | # define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
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538 | 558 | # define FLASH_CR_PER (1 << 1)
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539 | 559 | # define FLASH_CR_MER1 (1 << 2)
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540 | 560 | # define FLASH_CR_PNB_SHIFT (3)
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541 |
| -# define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT) |
| 561 | +# if defined(CONFIG_STM32_STM32G43XX) |
| 562 | +# define FLASH_CR_PNB_MASK (0x3f << FLASH_CR_PNB_SHIFT) |
| 563 | +# elif defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) |
| 564 | +# define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT) |
| 565 | +# elif defined(CONFIG_STM32_STM32G49XX) |
| 566 | +# define FLASH_CR_PNB_MASK (0xff << FLASH_CR_PNB_SHIFT) |
| 567 | +# endif |
542 | 568 | # define FLASH_CR_PNB(n) (((n) << FLASH_CR_PNB_SHIFT) & FLASH_CR_PNB_MASK)
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543 |
| -# define FLASH_CR_BKER (1 << 11) |
544 |
| -# define FLASH_CR_MER2 (1 << 15) |
| 569 | +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) |
| 570 | +# define FLASH_CR_BKER (1 << 11) |
| 571 | +# define FLASH_CR_MER2 (1 << 15) |
| 572 | +# endif |
545 | 573 | # define FLASH_CR_START (1 << 16)
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546 | 574 | # define FLASH_CR_OPTSTRT (1 << 17)
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547 | 575 | # define FLASH_CR_FSTPG (1 << 18)
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550 | 578 | # define FLASH_CR_RDERRIE (1 << 26)
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551 | 579 | # define FLASH_CR_OBL_LAUNCH (1 << 27)
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552 | 580 | # define FLASH_CR_SEC_PROT1 (1 << 28)
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553 |
| -# define FLASH_CR_SEC_PROT2 (1 << 29) |
| 581 | +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) |
| 582 | +# define FLASH_CR_SEC_PROT2 (1 << 29) |
| 583 | +# endif |
554 | 584 | # define FLASH_CR_OPTLOCK (1 << 30)
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555 | 585 | # define FLASH_CR_LOCK (1 << 31)
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556 | 586 | #endif
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568 | 598 | # define FLASH_ECCR_BK_ECC (1 << 21)
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569 | 599 | # define FLASH_ECCR_SYSF_ECC (1 << 22)
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570 | 600 | # define FLASH_ECCR_ECCIE (1 << 24)
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571 |
| -# define FLASH_ECCR_ECCC2 (1 << 28) |
572 |
| -# define FLASH_ECCR_ECCD2 (1 << 29) |
| 601 | +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) |
| 602 | +# define FLASH_ECCR_ECCC2 (1 << 28) |
| 603 | +# define FLASH_ECCR_ECCD2 (1 << 29) |
| 604 | +# endif |
573 | 605 | # define FLASH_ECCR_ECCC (1 << 30)
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574 | 606 | # define FLASH_ECCR_ECCD (1 << 31)
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575 | 607 | #endif
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633 | 665 | # define FLASH_OPTR_IWDG_STDBY (1 << 18)
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634 | 666 | # define FLASH_OPTR_WWDG_SW (1 << 19)
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635 | 667 | # define FLASH_OPTR_BFB2 (1 << 20)
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636 |
| -# define FLASH_OPTR_DBANK (1 << 22) |
| 668 | +# if defined(CONFIG_STM32_STM32G47XX) || defined (CONFIG_STM32_STM32G48XX) |
| 669 | +# define FLASH_OPTR_DBANK (1 << 22) |
| 670 | +# elif defined (CONFIG_STM32_STM32G49XX) |
| 671 | +# define FLASH_OPTR_PB4_PUPEN (1 << 22) |
| 672 | +# endif |
637 | 673 | # define FLASH_OPTR_NBOOT1 (1 << 23)
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638 | 674 | # define FLASH_OPTR_SRAM_PE (1 << 24)
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639 | 675 | # define FLASH_OPTR_CCMSRAM_RST (1 << 25)
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