fix up regs

Author: 2over12

macaw-aarch32/src/Data/Macaw/ARM/Arch.hs

@@ -393,7 +393,8 @@ instance MC.IsArchFn ARMPrimFn where
         let ppUnary s v' = s PP.<+> v'
             ppBinary s v1' v2' = s PP.<+> v1' PP.<+> v2'
             ppTernary s v1' v2' v3' = s PP.<+> v1' PP.<+> v2' PP.<+> v3'
-            ppSC s imm r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 = s PP.<+> PP.viaShow imm PP.<+> r0 PP.<+> r1 PP.<+> r2 PP.<+> r3 PP.<+> r4 PP.<+> r5 PP.<+> r6 PP.<+> r7
+            ppSC s imm r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 = s PP.<+> PP.viaShow imm PP.<+> r0 PP.<+> r1 PP.<+> r2 PP.<+> r3 PP.<+> r4 PP.<+> r5 PP.<+> r6 PP.<+> r7 
+              PP.<+> r8 PP.<+> r9 PP.<+> r10 PP.<+> r11 PP.<+> r12 PP.<+> r13 PP.<+> r14
         in case f of
           ARMSyscall imm r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 ->
             ppSC "arm_syscall" imm <$> pp r0 <*> pp r1 <*> pp r2 <*> pp r3 <*> pp r4 <*> pp r5 <*> pp r6 <*> pp r7 <*> pp r8 <*> pp r9 <*> pp r10 <*> pp r11  <*> pp r12  <*> pp r13 <*> pp r14  
@@ -436,8 +437,9 @@ instance FCls.FoldableFC ARMPrimFn where
 instance FCls.TraversableFC ARMPrimFn where
   traverseFC go f =
     case f of
-      ARMSyscall imm r0 r1 r2 r3 r4 r5 r6 r7 ->
-        ARMSyscall imm <$> go r0 <*> go r1 <*> go r2 <*> go r3 <*> go r4 <*> go r5 <*> go r6 <*> go r7
+      ARMSyscall imm r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 ->
+        ARMSyscall imm <$> go r0 <*> go r1 <*> go r2 <*> go r3 <*> go r4 <*> go r5 <*> go r6 
+          <*> go r7 <*> go r8 <*> go r9 <*> go r10 <*> go r11 <*> go r12 <*> go r13 <*> go r14
       UDiv rep lhs rhs -> UDiv rep <$> go lhs <*> go rhs
       SDiv rep lhs rhs -> SDiv rep <$> go lhs <*> go rhs
       URem rep lhs rhs -> URem rep <$> go lhs <*> go rhs
@@ -567,8 +569,9 @@ rewritePrimFn :: ARMPrimFn (MC.Value ARM.AArch32 src) tp
               -> Rewriter ARM.AArch32 s src tgt (MC.Value ARM.AArch32 tgt tp)
 rewritePrimFn f =
   case f of
-    ARMSyscall imm r0 r1 r2 r3 r4 r5 r6 r7 -> do
+    ARMSyscall imm r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 -> do
       tgtFn <- ARMSyscall imm <$> rewriteValue r0 <*> rewriteValue r1 <*> rewriteValue r2 <*> rewriteValue r3 <*> rewriteValue r4 <*> rewriteValue r5 <*> rewriteValue r6 <*> rewriteValue r7
+        <*> rewriteValue r8 <*> rewriteValue r9 <*> rewriteValue r10 <*> rewriteValue r11 <*> rewriteValue r12 <*> rewriteValue r13 <*> rewriteValue r14
       evalRewrittenArchFn tgtFn
     UDiv rep lhs rhs -> do
       tgtFn <- UDiv rep <$> rewriteValue lhs <*> rewriteValue rhs
@@ -728,6 +731,13 @@ t32InstructionMatcher (ThumbDis.Instruction opc operands) =
                                    <*> G.getRegVal ARMReg.r5
                                    <*> G.getRegVal ARMReg.r6
                                    <*> G.getRegVal ARMReg.r7
+                                   <*> G.getRegVal ARMReg.r8
+                                   <*> G.getRegVal ARMReg.r9
+                                   <*> G.getRegVal ARMReg.r10
+                                   <*> G.getRegVal ARMReg.r11
+                                   <*> G.getRegVal ARMReg.r12
+                                   <*> G.getRegVal ARMReg.r13
+                                   <*> G.getRegVal ARMReg.r14
             res <- G.addExpr =<< evalArchFn sc
             -- res is a tuple of form (R1, R0).  This is reversed from the
             -- user provided return Assignment of empty :> R0 :> R1 because