@@ -1094,6 +1094,7 @@ void imag_on_non_glvalue() {
10941094// OGCG: %[[A_IMAG:.*]] = load float, ptr %[[A_IMAG_PTR]], align 4
10951095// OGCG: store float %[[A_IMAG]], ptr %[[B_ADDR]], align 4
10961096
1097+ <<<<<<< HEAD
10971098void atomic_complex_type () {
10981099 _Atomic (float _Complex ) a;
10991100 float _Complex b = __c11_atomic_load (&a, __ATOMIC_RELAXED);
@@ -1132,6 +1133,8 @@ void atomic_complex_type() {
11321133// OGCG: store float %[[ATOMIC_TMP_REAL]], ptr %[[B_REAL_PTR]], align 4
11331134// OGCG: store float %[[ATOMIC_TMP_IMAG]], ptr %[[B_IMAG_PTR]], align 4
11341135
1136+ =======
1137+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
11351138void real_on_scalar_glvalue() {
11361139 float a;
11371140 float b = __real__ a;
@@ -1140,8 +1143,12 @@ void real_on_scalar_glvalue() {
11401143// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a"]
11411144// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["b", init]
11421145// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.float>, !cir.float
1146+ <<<<<<< HEAD
11431147// CIR: %[[A_REAL:.*]] = cir.complex.real %[[TMP_A]] : !cir.float -> !cir.float
11441148// CIR: cir.store{{.*}} %[[A_REAL]], %[[B_ADDR]] : !cir.float, !cir.ptr<!cir.float>
1149+ =======
1150+ // CIR: cir.store{{.*}} %[[TMP_A]], %[[B_ADDR]] : !cir.float, !cir.ptr<!cir.float>
1151+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
11451152
11461153// LLVM: %[[A_ADDR:.*]] = alloca float, i64 1, align 4
11471154// LLVM: %[[B_ADDR:.*]] = alloca float, i64 1, align 4
@@ -1160,9 +1167,14 @@ void imag_on_scalar_glvalue() {
11601167
11611168// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a"]
11621169// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["b", init]
1170+ <<<<<<< HEAD
11631171// CIR: %[[TMP_A:.*]] = cir.load %[[A_ADDR]] : !cir.ptr<!cir.float>, !cir.float
11641172// CIR: %[[A_IMAG:.*]] = cir.complex.imag %[[TMP_A]] : !cir.float -> !cir.float
11651173// CIR: cir.store{{.*}} %[[A_IMAG]], %[[B_ADDR]] : !cir.float, !cir.ptr<!cir.float>
1174+ =======
1175+ // CIR: %[[CONST_ZERO:.*]] = cir.const #cir.fp<0.000000e+00> : !cir.float
1176+ // CIR: cir.store{{.*}} %[[CONST_ZERO]], %[[B_ADDR]] : !cir.float, !cir.ptr<!cir.float>
1177+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
11661178
11671179// LLVM: %[[A_ADDR:.*]] = alloca float, i64 1, align 4
11681180// LLVM: %[[B_ADDR:.*]] = alloca float, i64 1, align 4
@@ -1180,9 +1192,14 @@ void real_on_scalar_with_type_promotion() {
11801192// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["a"]
11811193// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["b", init]
11821194// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
1195+ <<<<<<< HEAD
11831196// CIR: %[[TMP_A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
11841197// CIR: %[[A_REAL:.*]] = cir.complex.real %[[TMP_A_F32]] : !cir.float -> !cir.float
11851198// CIR: %[[TMP_A_F16:.*]] = cir.cast floating %[[A_REAL]] : !cir.float -> !cir.f16
1199+ =======
1200+ // CIR: %[[TMP_A_F32:.*]] = cir.cast(floating, %[[TMP_A]] : !cir.f16), !cir.float
1201+ // CIR: %[[TMP_A_F16:.*]] = cir.cast(floating, %[[TMP_A_F32]] : !cir.float), !cir.f16
1202+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
11861203// CIR: cir.store{{.*}} %[[TMP_A_F16]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
11871204
11881205// LLVM: %[[A_ADDR:.*]] = alloca half, i64 1, align 2
@@ -1206,10 +1223,16 @@ void imag_on_scalar_with_type_promotion() {
12061223
12071224// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["a"]
12081225// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["b", init]
1226+ <<<<<<< HEAD
12091227// CIR: %[[TMP_A:.*]] = cir.load %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
12101228// CIR: %[[A_IMAG:.*]] = cir.complex.imag %[[TMP_A]] : !cir.f16 -> !cir.f16
12111229// CIR: %[[A_IMAG_F16:.*]] = cir.cast floating %[[A_IMAG]] : !cir.f16 -> !cir.f16
12121230// CIR: cir.store{{.*}} %[[A_IMAG_F16]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
1231+ =======
1232+ // CIR: %[[CONST_ZERO:.*]] = cir.const #cir.fp<0.000000e+00> : !cir.float
1233+ // CIR: %[[CONST_ZERO_F16:.*]] = cir.cast(floating, %[[CONST_ZERO]] : !cir.float), !cir.f16
1234+ // CIR: cir.store{{.*}} %[[CONST_ZERO_F16]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
1235+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
12131236
12141237// LLVM: %[[A_ADDR:.*]] = alloca half, i64 1, align 2
12151238// LLVM: %[[B_ADDR:.*]] = alloca half, i64 1, align 2
@@ -1227,8 +1250,13 @@ void imag_on_const_scalar() {
12271250// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a"]
12281251// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["b", init]
12291252// CIR: %[[CONST_ONE:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
1253+ <<<<<<< HEAD
12301254// CIR: %[[CONST_IMAG:.*]] = cir.complex.imag %[[CONST_ONE]] : !cir.float -> !cir.float
12311255// CIR: cir.store{{.*}} %[[CONST_IMAG]], %[[B_ADDR]] : !cir.float, !cir.ptr<!cir.float>
1256+ =======
1257+ // CIR: %[[CONST_ZERO:.*]] = cir.const #cir.fp<0.000000e+00> : !cir.float
1258+ // CIR: cir.store{{.*}} %[[CONST_ZERO]], %[[B_ADDR]] : !cir.float, !cir.ptr<!cir.float>
1259+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
12321260
12331261// LLVM: %[[A_ADDR:.*]] = alloca float, i64 1, align 4
12341262// LLVM: %[[B_ADDR:.*]] = alloca float, i64 1, align 4
@@ -1237,6 +1265,7 @@ void imag_on_const_scalar() {
12371265// OGCG: %[[A_ADDR:.*]] = alloca float, align 4
12381266// OGCG: %[[B_ADDR:.*]] = alloca float, align 4
12391267// OGCG: store float 0.000000e+00, ptr %[[B_ADDR]], align 4
1268+ <<<<<<< HEAD
12401269
12411270void real_on_scalar_from_real_with_type_promotion() {
12421271 _Float16 _Complex a;
@@ -1677,3 +1706,5 @@ void load_store_volatile_2() {
16771706// OGCG: %[[DV_IMAG_PTR:.*]] = getelementptr inbounds nuw { i32, i32 }, ptr %[[DV_ADDR]], i32 0, i32 1
16781707// OGCG: store volatile i32 %[[D_REAL]], ptr %[[DV_REAL_PTR]], align 4
16791708// OGCG: store volatile i32 %[[D_IMAG]], ptr %[[DV_IMAG_PTR]], align 4
1709+ =======
1710+ >>>>>>> c9042b8fa9e7 (Merge llvm/main into amd-debug)
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