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@@ -5,24 +5,26 @@ This subtree contains the ExecuTorch Backend implementation for the
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The eIQ® Neutron NPU is a highly scalable accelerator core architecture providing machine learning (ML) acceleration,
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able to support common and critical tasks for edge AI such as anomaly detection, speech recognition,
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image classification, object detection, facial recognition, image segmentation, and generative AI use cases like
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image classification, object detection, facial recognition, image segmentation, and generative AI use cases like
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large and small language models (LLMs & SLMs) and text-to-speech (TTS).
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The architecture provides power and performance optimized NPUs integrated with NXP's broad portfolio of
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The architecture provides power and performance optimized NPUs integrated with NXP's broad portfolio of
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microcontrollers and applications processors.
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The eIQ Neutron NPUs offer support for a wide variety of neural network types such as CNN, RNN, TCN and Transformer
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The eIQ Neutron NPUs offer support for a wide variety of neural network types such as CNN, RNN, TCN and Transformer
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networks, as well as the ability to adapt and scale to new model architectures, topologies and layer types introduced
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to AI workloads. ML application development with the eIQ Neutron NPU is fully supported by the
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to AI workloads. ML application development with the eIQ Neutron NPU is fully supported by the
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[eIQ machine learning software development environment](https://www.nxp.com/design/design-center/software/eiq-ml-development-environment/eiq-toolkit-for-end-to-end-model-development-and-deployment:EIQ-TOOLKIT).
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The eIQ AI SW Stack provides a streamlined development experience for developers and end-users of NXP products.
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eIQ extensions connect broader AI ecosystems to the edge, such as the NVIDIA TAO extension, which enables developers
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to bring AI models trained and fine-tuned with TAO to NXP-powered edge devices.
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## Supported NXP platforms
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At this moment following eIQ® Neutron NPU variants and NXP platforms are supported by the NXP eIQ Neutron Backend:
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***eIQ Neutron N3-64**, available on [i.MX RT700](https://www.nxp.com/products/i.MX-RT700)
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In the future the NXP eIQ Neutron Backend will be extended to support [i.MX 9 Application Processors](https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors:IMX9-PROCESSORS)
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In the future the NXP eIQ Neutron Backend will be extended to support [i.MX 9 Application Processors](https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors:IMX9-PROCESSORS)
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with eIQ Neutron NPU, like the [i.MX 95](https://www.nxp.com/products/iMX95).
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improvements. NXP and the ExecuTorch community is actively developing this codebase.
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## Neutron Backend implementation and SW architecture
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Neutron Backend uses the eIQ Neutron Converter as ML compiler to compile the delegated subgraph to Neutron microcode.
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Neutron Backend uses the eIQ Neutron Converter as ML compiler to compile the delegated subgraph to Neutron microcode.
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The Neutron Converter accepts the ML model in LiteRT format, for the **eIQ Neutron N3** class therefore the Neutron Backend
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uses the LiteRT flatbuffers format as IR between the ExecuTorch and Neutron Converter ML compiler.
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`node_conveters` is structured as single module for each Edge operator.
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*`backend/ir/lib` - automatically generated handlers from LiteRT flatbuffers schema.
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*`backend/ir/tflite_generator` and `backend/ir/tflite_optimizer` handle the serialization
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of the in-memory built subgraph for delegation into LiteRT/TFLite flatbuffers
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of the in-memory built subgraph for delegation into LiteRT/TFLite flatbuffers
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representation. Code taken from the onnx2tflite tool.
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*`edge_passes` - Various passes operating on Edge dialect level.
This project will guide you through the process of deploying your PTE model to the device.
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To get the MCUXpresso SDK follow this [guide](https://mcuxpresso.nxp.com/mcuxsdk/latest/html/middleware/eiq/executorch/docs/nxp/topics/getting_mcuxpresso.html),
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