Fix initialization of CR4_SMEP on x86_64

It used to be that secondary APs could not be initialized properly if they support `CR4_SMEP`. That is now fixed

Author: GrieferAtWork

kos/misc/magicemulator/qemu.dee

@@ -185,9 +185,19 @@ did_update_x86_64_kernel:
 				qemuExe = fs.joinpath(qemuExe, f"qemu-system-{TARGET_ARCH}");
 			break;
 		case "accel":
-			/* "-accel hax" breaks qemu's builtin GDB stub. :(
-			 * -> For now, ignore accel options if GDB is on. */
-			if (gdbMode != "emulator") {
+			/* "-accel *" breaks qemu's builtin GDB stub. :(
+			 *
+			 * -> For now, ignore accel options if GDB is on.
+			 *
+			 * On x86_64:
+			 *    GDB keeps truncating registers to 32-bits, which makes debugging pretty much impossible
+			 * On i386:
+			 *    Breakpoints don't seem to work. Though you can manually pause execution, at which point
+			 *    everything else seems to be working.
+			 */
+			if (gdbMode == "emulator") {
+				/* ... */
+			} else {
 				qemuArgs.extend({ "-accel", arg });
 			}
 			break;

kos/src/kernel/core/arch/i386/boot/_start64.S

@@ -700,6 +700,8 @@ INTERN_FUNCTION(_start)
 	movl   $(pagedir_kernel_phys), %eax
 	movl   %eax, %cr3
 
+
+
 	/* Configure the %CR4 register. */
 	movl   %cr4, %eax
 	/* Enable PageSizeExtension (required for 2Mib pages & long-mode),
@@ -712,19 +714,24 @@ INTERN_FUNCTION(_start)
 	jz     1f
 	orl    $(CR4_PGE), %eax
 1:
-	/* Enable SMAP if supported by the host (optional feature) */
+
+	/* Enable SMEP if supported by the host (optional feature) */
 	ttest  mask=CPUID_7B_SMEP, loc=(V2P(bootcpu_x86_cpuid) + OFFSET_CPUID_7B)
 	jz     1f
 	orl    $(CR4_SMEP), %eax
 1:
+
 	/* Enable FSGSBASE if supported by the host (emulated if unsupported) */
 	ttest  mask=CPUID_7B_FSGSBASE, loc=(V2P(bootcpu_x86_cpuid) + OFFSET_CPUID_7B)
 	jz     1f
 	orl    $(CR4_FSGSBASE), %eax
 1:
+
 	/* Save the fully configured CR4 register. */
 	movl   %eax, %cr4
 
+
+
 	/* Set the LME bit in the EFER MSR register. */
 	movl   $(IA32_EFER), %ecx
 	rdmsr
@@ -739,6 +746,7 @@ INTERN_FUNCTION(_start)
 	orl    $(IA32_EFER_SCE), %eax
 1:	wrmsr  /* Save the new configuration. */
 
+
 	/* Now to actually enable paging! */
 	movl  %cr0, %eax
 	orl   $(CR0_PG | CR0_WP), %eax

kos/src/kernel/core/arch/i386/sched/smp.S

@@ -615,6 +615,21 @@ PRIVATE_FUNCTION(x86_smp_init_cpuid)
 .Lsmp_ini_crN_donefpu:
 #endif /* CONFIG_HAVE_FPU */
 
+	/* If supported, enable SMEP now that we're in 64-bit, high-memory mode
+	 * This can only be done **after** we jumped to high memory, since  the
+	 * we were previously running off of this mapping:
+	 * >> 00000000009E8000-00000000009E8FFF: 00000000009E8000+4KiB      [xwu-adp][0]
+	 * Since this mapping is in what is normally user-space, it has the "u"
+	 * flag. And since SMEP causes the kernel to fault when trying to execute
+	 * user-space code, we had to wait until we got here:
+	 * >> FFFFFFFF809E8000-FFFFFFFF809EBFFF: 00000000009E8000+16KiB     [xw-gadp][0]
+	 */
+	ttest  mask=CPUID_7B_SMEP, loc=(thiscpu_x86_cpuid + OFFSET_CPUID_7B)(R_CPU)
+	jz     1f
+	orP    $(CR4_SMEP), %Pcx
+1:
+
+
 	/* Store results */
 	EXTERN(thiscpu_x86_saved_cr0)
 	movP   %Pax, thiscpu_x86_saved_cr0(R_CPU)
@@ -700,7 +715,7 @@ INTERN_FUNCTION(x86_smp_entry32)
 	ttest  mask=CPUID_1D_MSR, loc=%edx
 	jz     x86_smp_boot_failure_no_msr
 
-	/* Configure the %CR4 register. */
+	/* Configure the %CR4 register (except for `CR4_SMEP') */
 	movl   %cr4, %esp
 	/* Enable PageSizeExtension (required for 2Mib pages & long-mode),
 	 * as well as  PhysicalAddressExtension (required  for the  48-bit
@@ -717,13 +732,17 @@ INTERN_FUNCTION(x86_smp_entry32)
 	xorl   %eax, %eax
 	cpuid
 	cmpl   $(7), %eax
-	jnae   2f
+	jnae   2f /* if (!(%eax >= 7)) goto 2f */
 	movl   $(7), %eax
+	movl   $(0), %ecx /* Sub-leaf:0 */
 	cpuid
+#if 0 /* This can only be enabled once we're in 64-bit mode! */
 	ttest  mask=CPUID_7B_SMEP, loc=%ebx /* Enable SMAP if supported by the host (optional feature) */
 	jz     1f
 	orl    $(CR4_SMEP), %esp
-1:	ttest  mask=CPUID_7B_FSGSBASE, loc=%ebx /* Enable FSGSBASE if supported by the host (emulated if unsupported) */
+1:
+#endif
+	ttest  mask=CPUID_7B_FSGSBASE, loc=%ebx /* Enable FSGSBASE if supported by the host (emulated if unsupported) */
 	jz     1f
 	orl    $(CR4_FSGSBASE), %esp
 1:
@@ -778,12 +797,6 @@ INTERN_FUNCTION(x86_smp_entry32)
 	rdmsr
 	orl    $(IA32_EFER_NXE), %eax
 	wrmsr
-	/* With PAE + NX, try to enable its effects while
-	 * in kernel-space  (if  supported  by  the  CPU) */
-	ttest  mask=CPUID_7B_SMEP, loc=(bootcpu_x86_cpuid + OFFSET_CPUID_7B)
-	jz     1f
-	orl    $(CR4_SMEP), %esp
-1:
 #endif /* !CONFIG_NO_KERNEL_X86_PAGING_PAE */
 	/* Enable PGE support (if necessary for setting the page directory) */
 	ttest  mask=CPUID_1D_PGE, loc=((bootcpu_x86_cpuid - KERNEL_CORE_BASE) + OFFSET_CPUID_1D)