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GrumpyOldPizzaGrumpyOldPizza
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Properly keep the PWR module disabled unless access is needed
1 parent 796660f commit 5b7b348

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4 files changed

+110
-34
lines changed

4 files changed

+110
-34
lines changed

‎system/libstm32l4_dragonfly/USB/usbd_conf.c‎

Lines changed: 28 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -143,22 +143,25 @@ void OTG_FS_IRQHandler(void)
143143
*/
144144
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
145145
{
146+
uint32_t apb1enr1;
147+
146148
stm32l4_system_clk48_enable();
147149

148150
/* Peripheral clock enable */
149151
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
150152

151-
/* Enable VDDUSB */
152-
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
153-
{
154-
__HAL_RCC_PWR_CLK_ENABLE();
155-
PWR->CR2 |= PWR_CR2_USV;
156-
__HAL_RCC_PWR_CLK_DISABLE();
157-
}
158-
else
159-
{
160-
PWR->CR2 |= PWR_CR2_USV;
161-
}
153+
/* Enable VUSB */
154+
apb1enr1 = RCC->APB1ENR1;
155+
156+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN)) {
157+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
158+
}
159+
160+
PWR->CR2 |= PWR_CR2_USV;
161+
162+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN)) {
163+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
164+
}
162165

163166
/* Enable USB FS Interrupt */
164167
NVIC_EnableIRQ(OTG_FS_IRQn);
@@ -171,17 +174,20 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
171174
*/
172175
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
173176
{
174-
/* Disable VDDUSB */
175-
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
176-
{
177-
__HAL_RCC_PWR_CLK_ENABLE();
178-
PWR->CR2 &= ~PWR_CR2_USV;
179-
__HAL_RCC_PWR_CLK_DISABLE();
180-
}
181-
else
182-
{
183-
PWR->CR2 &= ~PWR_CR2_USV;
184-
}
177+
uint32_t apb1enr1;
178+
179+
/* Disable VUSB */
180+
apb1enr1 = RCC->APB1ENR1;
181+
182+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN)) {
183+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
184+
}
185+
186+
PWR->CR2 &= ~PWR_CR2_USV;
187+
188+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN)) {
189+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
190+
}
185191

186192
/* Peripheral clock disable */
187193
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();

‎system/libstm32l4_dragonfly/stm32l4_system.c‎

Lines changed: 80 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -251,11 +251,18 @@ void stm32l4_system_periph_disable(unsigned int periph)
251251

252252
static void stm32l4_system_msi4_sysclk(void)
253253
{
254+
uint32_t apb1enr1;
255+
254256
FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_4WS;
255257

256258
/* Select the proper voltage range */
257259

258-
RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
260+
apb1enr1 = RCC->APB1ENR1;
261+
262+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
263+
{
264+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
265+
}
259266

260267
if (PWR->CR1 & PWR_CR1_LPR)
261268
{
@@ -272,6 +279,11 @@ static void stm32l4_system_msi4_sysclk(void)
272279
{
273280
}
274281

282+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
283+
{
284+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
285+
}
286+
275287
/* Select the HSI as system clock source */
276288
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSI;
277289

@@ -355,7 +367,7 @@ void stm32l4_system_bootloader(void)
355367
RCC->AHB1ENR = RCC_AHB1ENR_FLASHEN;
356368
RCC->AHB2ENR = 0;
357369
RCC->AHB3ENR = 0;
358-
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
370+
RCC->APB1ENR1 = 0;
359371
RCC->APB1ENR2 = 0;
360372
RCC->APB2ENR = RCC_APB2ENR_SYSCFGEN;
361373
RCC->CCIPR = 0;
@@ -371,8 +383,6 @@ void stm32l4_system_bootloader(void)
371383

372384
stm32l4_system_msi4_sysclk();
373385

374-
RCC->APB1ENR1 &= ~RCC_APB1ENR1_PWREN;
375-
376386
/* Disable and clear pending interrupts (80 vectors).
377387
*/
378388
SysTick->CTRL = 0;
@@ -408,6 +418,7 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
408418
{
409419
uint32_t fclk, fvco, fpll, fpllout, mout, nout, rout, n, r;
410420
uint32_t count, msirange, hpre, ppre1, ppre2, latency;
421+
uint32_t apb1enr1;
411422

412423
if (!clk48 && ((sysclk <= 24000000) && stm32l4_system_device.clk48))
413424
{
@@ -424,7 +435,12 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
424435

425436
if (stm32l4_system_device.lseclk == 0)
426437
{
427-
RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
438+
apb1enr1 = RCC->APB1ENR1;
439+
440+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
441+
{
442+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
443+
}
428444

429445
PWR->CR1 |= PWR_CR1_DBP;
430446

@@ -441,6 +457,11 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
441457
SYSCFG->MEMRMP = (SYSCFG->MEMRMP & ~SYSCFG_MEMRMP_MEM_MODE) | SYSCFG_MEMRMP_MEM_MODE_0;
442458
RCC->APB2ENR &= ~RCC_APB2ENR_SYSCFGEN;
443459

460+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
461+
{
462+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
463+
}
464+
444465
SCB->VTOR = 0;
445466

446467
/* This needs to be assembly code as GCC catches NULL
@@ -493,7 +514,10 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
493514
*/
494515
PWR->CR4 |= PWR_CR4_VBE;
495516

496-
RCC->APB1ENR1 &= ~RCC_APB1ENR1_PWREN;
517+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
518+
{
519+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
520+
}
497521
}
498522

499523
if (stm32l4_system_device.hseclk == 0)
@@ -634,7 +658,12 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
634658
/* First switch to HSI as system clock.
635659
*/
636660

637-
RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
661+
apb1enr1 = RCC->APB1ENR1;
662+
663+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
664+
{
665+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
666+
}
638667

639668
/* Select Range 1 to switch clocks */
640669

@@ -850,7 +879,10 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
850879
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | latency;
851880
}
852881

853-
RCC->APB1ENR1 &= ~RCC_APB1ENR1_PWREN;
882+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
883+
{
884+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
885+
}
854886

855887
stm32l4_system_device.sysclk = sysclk;
856888
stm32l4_system_device.hclk = hclk;
@@ -952,6 +984,8 @@ uint32_t stm32l4_system_pclk2(void)
952984

953985
bool stm32l4_system_suspend(void)
954986
{
987+
uint32_t apb1enr1;
988+
955989
/* #### Add code here that calls STOP_ENTER, and if that fails calls out STOP_CANCEL */
956990

957991
/* Disable FLASH in sleep/deepsleep */
@@ -1017,11 +1051,19 @@ bool stm32l4_system_suspend(void)
10171051

10181052
/* Set up STOP1 */
10191053

1020-
RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
1054+
apb1enr1 = RCC->APB1ENR1;
10211055

1056+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
1057+
{
1058+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
1059+
}
1060+
10221061
PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS) | PWR_CR1_LPMS_STOP1;
10231062

1024-
RCC->APB1ENR1 &= ~RCC_APB1ENR1_PWREN;
1063+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
1064+
{
1065+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
1066+
}
10251067

10261068
return true;
10271069
}
@@ -1102,16 +1144,28 @@ bool stm32l4_system_stop(void)
11021144

11031145
bool stm32l4_system_standby(void)
11041146
{
1105-
/* #### Add code here that calls STANDBY_ENTER, and if that fails calls out STANDBY_CANCEL */
1147+
uint32_t apb1enr1;
11061148

1107-
RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
1149+
/* #### Add code here that calls STANDBY_ENTER, and if that fails calls out STANDBY_CANCEL */
11081150

11091151
/* ERRATA 2.1.15. WAR: Switch MSI to 4MHz before entering low power mode */
11101152

11111153
stm32l4_system_msi4_sysclk();
11121154

1155+
apb1enr1 = RCC->APB1ENR1;
1156+
1157+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
1158+
{
1159+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
1160+
}
1161+
11131162
PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS) | PWR_CR1_LPMS_STANDBY;
11141163

1164+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
1165+
{
1166+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
1167+
}
1168+
11151169
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
11161170

11171171
__WFI();
@@ -1121,14 +1175,28 @@ bool stm32l4_system_standby(void)
11211175

11221176
bool stm32l4_system_shutdown(void)
11231177
{
1178+
uint32_t apb1enr1;
1179+
11241180
/* #### Add code here that calls SHUTDOWN_ENTER, and if that fails calls out SHUTDOWN_CANCEL */
11251181

11261182
/* ERRATA 2.1.15. WAR: Switch MSI to 4MHz before entering low power mode */
11271183

11281184
stm32l4_system_msi4_sysclk();
11291185

1186+
apb1enr1 = RCC->APB1ENR1;
1187+
1188+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
1189+
{
1190+
armv7m_atomic_or(&RCC->APB1ENR1, RCC_APB1ENR1_PWREN);
1191+
}
1192+
11301193
PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS) | PWR_CR1_LPMS_SHUTDOWN;
11311194

1195+
if (!(apb1enr1 & RCC_APB1ENR1_PWREN))
1196+
{
1197+
armv7m_atomic_and(&RCC->APB1ENR1, ~RCC_APB1ENR1_PWREN);
1198+
}
1199+
11321200
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
11331201

11341202
__WFI();

‎system/libstm32l4_dragonfly/system_stm32l4xx.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,8 @@ void SystemInit(void)
220220
/* Disable all interrupts */
221221
RCC->CIER = 0x00000000;
222222

223+
RCC->APB1ENR1 &= ~RCC_APB1ENR1_PWREN;
224+
223225
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
224226
SYSCFG->MEMRMP = (SYSCFG->MEMRMP & ~SYSCFG_MEMRMP_MEM_MODE);
225227
RCC->APB2ENR &= ~RCC_APB2ENR_SYSCFGEN;

‎variants/dragonfly/libstm32l4_dragonfly.a‎

2.08 KB
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