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#include "stm32l4xx.h"
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#include "stm32l4_dma.h"
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+ #include "stm32l4_system.h"
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#include "armv7m.h"
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@@ -73,45 +74,28 @@ static const IRQn_Type stm32l4_dma_interrupt_table[16] = {
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};
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typedef struct _stm32l4_dma_driver_t {
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+ stm32l4_dma_t * instances [16 ];
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volatile uint32_t mask ;
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volatile uint32_t flash ;
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- stm32l4_dma_t * instances [16 ];
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+ volatile uint32_t dma1 ;
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+ volatile uint32_t dma2 ;
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} stm32l4_dma_driver_t ;
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static stm32l4_dma_driver_t stm32l4_dma_driver ;
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- static void stm32l4_dma_track (uint32_t address )
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+ static inline void stm32l4_dma_track (uint32_t channel , uint32_t address )
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{
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if (address < 0x10000000 )
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{
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- armv7m_atomic_add (& stm32l4_dma_driver .flash , 1 );
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-
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- armv7m_atomic_or (& RCC -> AHB1SMENR , RCC_AHB1SMENR_FLASHSMEN );
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+ stm32l4_system_periph_cond_wake (SYSTEM_PERIPH_FLASH , & stm32l4_dma_driver .flash , (1ul << channel ));
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}
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}
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- static void stm32l4_dma_untrack (uint32_t address )
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+ static inline void stm32l4_dma_untrack (uint32_t channel , uint32_t address )
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{
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- uint32_t o_flash , n_flash ;
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-
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if (address < 0x10000000 )
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{
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- o_flash = stm32l4_dma_driver .flash ;
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-
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- do
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- {
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- n_flash = o_flash - 1 ;
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-
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- if (n_flash == 0 )
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- {
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- armv7m_atomic_and (& RCC -> AHB1SMENR , ~RCC_AHB1SMENR_FLASHSMEN );
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- }
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- else
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- {
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- armv7m_atomic_or (& RCC -> AHB1SMENR , RCC_AHB1SMENR_FLASHSMEN );
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- }
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- }
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- while (!armv7m_atomic_compare_exchange (& stm32l4_dma_driver .flash , & o_flash , n_flash ));
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+ stm32l4_system_periph_cond_sleep (SYSTEM_PERIPH_FLASH , & stm32l4_dma_driver .flash , (1ul << channel ));
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}
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}
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@@ -192,12 +176,14 @@ void stm32l4_dma_enable(stm32l4_dma_t *dma, stm32l4_dma_callback_t callback, voi
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if (!(dma -> channel & 8 ))
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{
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- armv7m_atomic_or (& RCC -> AHB1ENR , RCC_AHB1ENR_DMA1EN );
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+ stm32l4_system_periph_cond_enable (SYSTEM_PERIPH_DMA1 , & stm32l4_dma_driver .dma1 , (1ul << (dma -> channel & 7 )));
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+
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armv7m_atomic_modify (& DMA1_CSELR -> CSELR , (15 << shift ), (dma -> channel >> 4 ) << shift );
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}
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else
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{
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- armv7m_atomic_or (& RCC -> AHB1ENR , RCC_AHB1ENR_DMA2EN );
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+ stm32l4_system_periph_cond_enable (SYSTEM_PERIPH_DMA2 , & stm32l4_dma_driver .dma2 , (1ul << (dma -> channel & 7 )));
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+
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armv7m_atomic_modify (& DMA2_CSELR -> CSELR , (15 << shift ), (dma -> channel >> 4 ) << shift );
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}
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@@ -215,7 +201,16 @@ void stm32l4_dma_disable(stm32l4_dma_t *dma)
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NVIC_DisableIRQ (dma -> interrupt );
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- stm32l4_dma_untrack (DMA -> CMAR );
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+ stm32l4_dma_untrack (dma -> channel , DMA -> CMAR );
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+
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+ if (!(dma -> channel & 8 ))
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+ {
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+ stm32l4_system_periph_cond_disable (SYSTEM_PERIPH_DMA1 , & stm32l4_dma_driver .dma1 , (1ul << (dma -> channel & 7 )));
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+ }
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+ else
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+ {
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+ stm32l4_system_periph_cond_disable (SYSTEM_PERIPH_DMA2 , & stm32l4_dma_driver .dma2 , (1ul << (dma -> channel & 7 )));
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+ }
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}
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void stm32l4_dma_start (stm32l4_dma_t * dma , uint32_t tx_data , uint32_t rx_data , uint16_t xf_count , uint32_t option )
@@ -236,18 +231,18 @@ void stm32l4_dma_start(stm32l4_dma_t *dma, uint32_t tx_data, uint32_t rx_data, u
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DMA2 -> IFCR = (15 << shift );
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}
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- stm32l4_dma_untrack (DMA -> CMAR );
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+ stm32l4_dma_untrack (dma -> channel , DMA -> CMAR );
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if (option & DMA_OPTION_MEMORY_TO_PERIPHERAL )
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{
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- stm32l4_dma_track (rx_data );
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+ stm32l4_dma_track (dma -> channel , rx_data );
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DMA -> CMAR = rx_data ;
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DMA -> CPAR = tx_data ;
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}
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else
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{
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- stm32l4_dma_track (tx_data );
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+ stm32l4_dma_track (dma -> channel , tx_data );
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DMA -> CMAR = tx_data ;
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DMA -> CPAR = rx_data ;
@@ -265,7 +260,7 @@ uint16_t stm32l4_dma_stop(stm32l4_dma_t *dma)
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DMA -> CCR &= ~(DMA_CCR_EN | DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_TEIE );
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- stm32l4_dma_untrack (DMA -> CMAR );
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+ stm32l4_dma_untrack (dma -> channel , DMA -> CMAR );
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DMA -> CMAR = 0xffffffff ;
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