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[RISCV] Add compress patterns for Xqcibi branch instructions (llvm#143095)
This patch adds patterns to compress from the 48-bit qc.e.bxxi to the 32 bit qc.bxxi branch instructions.
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5 files changed

+174
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lines changed

5 files changed

+174
-41
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -341,21 +341,33 @@ def simm12 : RISCVSImmLeafOp<12> {
341341
def simm12_no6 : ImmLeaf<XLenVT, [{
342342
return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;
343343

344-
// A 13-bit signed immediate where the least significant bit is zero.
345-
def bare_simm13_lsb0 : Operand<OtherVT> {
346-
let ParserMatchClass = BareSImmNLsb0AsmOperand<13>;
347-
let PrintMethod = "printBranchOperand";
348-
let EncoderMethod = "getImmOpValueAsrN<1>";
349-
let DecoderMethod = "decodeSImmOperandAndLslN<13, 1>";
344+
class BareSImm13Lsb0MaybeSym : Operand<OtherVT> {
350345
let MCOperandPredicate = [{
351346
int64_t Imm;
352347
if (MCOp.evaluateAsConstantImm(Imm))
353348
return isShiftedInt<12, 1>(Imm);
354349
return MCOp.isBareSymbolRef();
355350
}];
351+
}
352+
353+
// A 13-bit signed immediate where the least significant bit is zero. The ImmLeaf
354+
// is needed so that the CompressInstEmitter can correctly add checks for the
355+
// compress patterns that involve instructions that use this operand. Similar to
356+
// bare_simm9_lsb0 in RISCVInstrInfoC.td.
357+
def bare_simm13_lsb0 : BareSImm13Lsb0MaybeSym,
358+
ImmLeaf<XLenVT, [{return isShiftedInt<12, 1>(Imm);}]> {
359+
let ParserMatchClass = BareSImmNLsb0AsmOperand<13>;
360+
let PrintMethod = "printBranchOperand";
361+
let EncoderMethod = "getImmOpValueAsrN<1>";
362+
let DecoderMethod = "decodeSImmOperandAndLslN<13, 1>";
356363
let OperandType = "OPERAND_PCREL";
357364
}
358365

366+
// We need this (sort of) duplicate definition since adding ImmLeaf to
367+
// bare_simm13_lsb0 above makes it not sit well with codegen patterns where it
368+
// is used to match with a basic block (eg. BccPat<>).
369+
def bare_simm13_lsb0_bb : BareSImm13Lsb0MaybeSym;
370+
359371
class UImm20OperandMaybeSym : RISCVUImmOp<20> {
360372
let MCOperandPredicate = [{
361373
int64_t Imm;
@@ -1660,10 +1672,10 @@ multiclass SelectCC_GPR_riirr<DAGOperand valty, DAGOperand imm> {
16601672
// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
16611673
multiclass BccPat<CondCode Cond, RVInstB Inst> {
16621674
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), GPR:$rs2, Cond, bb:$imm12),
1663-
(Inst GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12)>;
1675+
(Inst GPR:$rs1, GPR:$rs2, bare_simm13_lsb0_bb:$imm12)>;
16641676
// Explicitly select 0 to X0. The register coalescer doesn't always do it.
16651677
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), 0, Cond, bb:$imm12),
1666-
(Inst GPR:$rs1, (XLenVT X0), bare_simm13_lsb0:$imm12)>;
1678+
(Inst GPR:$rs1, (XLenVT X0), bare_simm13_lsb0_bb:$imm12)>;
16671679
}
16681680

16691681
class BrccCompressOpt<CondCode Cond, RVInstB Inst>

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -798,9 +798,9 @@ def IntCCtoRISCVCCCV : SDNodeXForm<riscv_selectcc, [{
798798

799799
let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
800800
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
801-
(CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
801+
(CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
802802
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
803-
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
803+
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0_bb:$imm12)>;
804804

805805
defm CC_SImm5_CV : SelectCC_GPR_riirr<GPR, simm5>;
806806

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 29 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,12 @@ def uimm5nonzero : RISCVOp<XLenVT>,
1919
let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
2020
let DecoderMethod = "decodeUImmNonZeroOperand<5>";
2121
let OperandType = "OPERAND_UIMM5_NONZERO";
22+
let MCOperandPredicate = [{
23+
int64_t Imm;
24+
if (!MCOp.evaluateAsConstantImm(Imm))
25+
return false;
26+
return (Imm != 0) && isUInt<5>(Imm);;
27+
}];
2228
}
2329

2430
def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
@@ -111,6 +117,12 @@ def simm5nonzero : RISCVOp<XLenVT>,
111117
let ParserMatchClass = SImmAsmOperand<5, "NonZero">;
112118
let DecoderMethod = "decodeSImmNonZeroOperand<5>";
113119
let OperandType = "OPERAND_SIMM5_NONZERO";
120+
let MCOperandPredicate = [{
121+
int64_t Imm;
122+
if (!MCOp.evaluateAsConstantImm(Imm))
123+
return false;
124+
return (Imm != 0) && isInt<5>(Imm);
125+
}];
114126
}
115127

116128
def simm11 : RISCVSImmLeafOp<11>;
@@ -1322,11 +1334,11 @@ class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
13221334
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
13231335
class BcciPat<CondCode Cond, QCIBranchInst_rii Inst, DAGOperand InTyImm>
13241336
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
1325-
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
1337+
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0_bb:$imm12)>;
13261338

13271339
class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
13281340
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
1329-
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
1341+
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0_bb:$imm12)>;
13301342

13311343
defm CC_SImm5NonZero_QC : SelectCC_GPR_riirr<GPRNoX0, simm5nonzero>;
13321344
defm CC_UImm5NonZero_QC : SelectCC_GPR_riirr<GPRNoX0, uimm5nonzero>;
@@ -1543,3 +1555,18 @@ def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
15431555
def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
15441556
(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
15451557
} // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
1558+
1559+
let isCompressOnly = true, Predicates = [HasVendorXqcibi, IsRV32] in {
1560+
def : CompressPat<(QC_E_BEQI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
1561+
(QC_BEQI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
1562+
def : CompressPat<(QC_E_BNEI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
1563+
(QC_BNEI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
1564+
def : CompressPat<(QC_E_BGEI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
1565+
(QC_BGEI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
1566+
def : CompressPat<(QC_E_BLTI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
1567+
(QC_BLTI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
1568+
def : CompressPat<(QC_E_BGEUI GPRNoX0:$rs1, uimm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
1569+
(QC_BGEUI GPRNoX0:$rs1, uimm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
1570+
def : CompressPat<(QC_E_BLTUI GPRNoX0:$rs1, uimm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
1571+
(QC_BLTUI GPRNoX0:$rs1, uimm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
1572+
} // let isCompressOnly = true, Predicates = [HasVendorXqcibi, IsRV32]

‎llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s‎

Lines changed: 74 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -64,59 +64,115 @@ test:
6464
.L6:
6565
ret
6666

67-
# CHECK-INST: qc.e.beqi a0, 0x1, 0x7a26
67+
# CHECK-INST: qc.e.beqi a0, 0x51, 0x7a26
6868
# CHECK-INST-NEXT: jal zero, 0x8e76
69-
# CHECK-INST-RELAX: qc.e.beqi a0, 0x1, 0x7a26
69+
# CHECK-INST-RELAX: qc.e.beqi a0, 0x51, 0x7a26
7070
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
71-
qc.e.bnei a0, 1, .L7
71+
qc.e.bnei a0, 81, .L7
7272
.fill 1300, 4, 0
7373
.L7:
7474
ret
7575

76-
# CHECK-INST: qc.e.bnei a0, 0x2, 0x8e82
76+
# CHECK-INST: qc.e.bnei a0, 0x3e, 0x8e82
7777
# CHECK-INST-NEXT: jal zero, 0xa2d2
78-
# CHECK-INST-RELAX: qc.e.bnei a0, 0x2, 0x8e82
78+
# CHECK-INST-RELAX: qc.e.bnei a0, 0x3e, 0x8e82
7979
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
80-
qc.e.beqi a0, 2, .L8
80+
qc.e.beqi a0, 62, .L8
8181
.fill 1300, 4, 0
8282
.L8:
8383
ret
8484

85-
# CHECK-INST: qc.e.bgei a0, 0x3, 0xa2de
85+
# CHECK-INST: qc.e.bgei a0, 0x5d, 0xa2de
8686
# CHECK-INST-NEXT: jal zero, 0xb72e
87-
# CHECK-INST-RELAX: qc.e.bgei a0, 0x3, 0xa2de
87+
# CHECK-INST-RELAX: qc.e.bgei a0, 0x5d, 0xa2de
8888
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
89-
qc.e.blti a0, 3, .L9
89+
qc.e.blti a0, 93, .L9
9090
.fill 1300, 4, 0
9191
.L9:
9292
ret
9393

94-
# CHECK-INST: qc.e.blti a0, 0x4, 0xb73a
94+
# CHECK-INST: qc.e.blti a0, 0x2c, 0xb73a
9595
# CHECK-INST-NEXT: jal zero, 0xcb8a
96-
# CHECK-INST-RELAX: qc.e.blti a0, 0x4, 0xb73a
96+
# CHECK-INST-RELAX: qc.e.blti a0, 0x2c, 0xb73a
9797
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
98-
qc.e.bgei a0, 4, .L10
98+
qc.e.bgei a0, 44, .L10
9999
.fill 1300, 4, 0
100100
.L10:
101101
ret
102102

103-
# CHECK-INST: qc.e.bgeui a0, 0x5, 0xcb96
103+
# CHECK-INST: qc.e.bgeui a0, 0x37, 0xcb96
104104
# CHECK-INST-NEXT: jal zero, 0xdfe6
105-
# CHECK-INST-RELAX: qc.e.bgeui a0, 0x5, 0xcb96
105+
# CHECK-INST-RELAX: qc.e.bgeui a0, 0x37, 0xcb96
106106
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
107-
qc.e.bltui a0, 5, .L11
107+
qc.e.bltui a0, 55, .L11
108108
.fill 1300, 4, 0
109109
.L11:
110110
ret
111111

112-
# CHECK-INST: qc.e.bltui a0, 0x6, 0xdff2
112+
# CHECK-INST: qc.e.bltui a0, 0x24, 0xdff2
113113
# CHECK-INST-NEXT: jal zero, 0xf442
114-
# CHECK-INST-RELAX: qc.e.bltui a0, 0x6, 0xdff2
114+
# CHECK-INST-RELAX: qc.e.bltui a0, 0x24, 0xdff2
115115
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
116-
qc.e.bgeui a0, 6, .L12
116+
qc.e.bgeui a0, 36, .L12
117117
.fill 1300, 4, 0
118118
.L12:
119119
ret
120120

121+
# Check that instructions are first compressed and then relaxed
122+
123+
# CHECK-INST: qc.beqi a0, 0xa, 0xf44c
124+
# CHECK-INST-NEXT: jal zero, 0x1089c
125+
# CHECK-INST-RELAX: qc.beqi a0, 0xa, 0xf44c
126+
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
127+
qc.e.bnei a0, 10, .L13
128+
.fill 1300, 4, 0
129+
.L13:
130+
ret
131+
132+
# CHECK-INST: qc.bnei a0, 0xa, 0x108a6
133+
# CHECK-INST-NEXT: jal zero, 0x11cf6
134+
# CHECK-INST-RELAX: qc.bnei a0, 0xa, 0x108a6
135+
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
136+
qc.e.beqi a0, 10, .L14
137+
.fill 1300, 4, 0
138+
.L14:
139+
ret
140+
141+
# CHECK-INST: qc.bgei a0, 0xa, 0x11d00
142+
# CHECK-INST-NEXT: jal zero, 0x13150
143+
# CHECK-INST-RELAX: qc.bgei a0, 0xa, 0x11d00
144+
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
145+
qc.e.blti a0, 10, .L15
146+
.fill 1300, 4, 0
147+
.L15:
148+
ret
149+
150+
# CHECK-INST: qc.blti a0, 0xa, 0x1315a
151+
# CHECK-INST-NEXT: jal zero, 0x145aa
152+
# CHECK-INST-RELAX: qc.blti a0, 0xa, 0x1315a
153+
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
154+
qc.e.bgei a0, 10, .L16
155+
.fill 1300, 4, 0
156+
.L16:
157+
ret
158+
159+
# CHECK-INST: qc.bgeui a0, 0xa, 0x145b4
160+
# CHECK-INST-NEXT: jal zero, 0x15a04
161+
# CHECK-INST-RELAX: qc.bgeui a0, 0xa, 0x145b4
162+
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
163+
qc.e.bltui a0, 10, .L17
164+
.fill 1300, 4, 0
165+
.L17:
166+
ret
167+
168+
# CHECK-INST: qc.bltui a0, 0xa, 0x15a0e
169+
# CHECK-INST-NEXT: jal zero, 0x16e5e
170+
# CHECK-INST-RELAX: qc.bltui a0, 0xa, 0x15a0e
171+
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
172+
qc.e.bgeui a0, 10, .L18
173+
.fill 1300, 4, 0
174+
.L18:
175+
ret
176+
121177
.Lfunc_end0:
122178
.size test, .Lfunc_end0-test

‎llvm/test/MC/RISCV/xqcibi-valid.s‎

Lines changed: 49 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
# Xqcibi - Qualcomm uC Branch Immediate Extension
22
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibi -M no-aliases -show-encoding \
3-
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
3+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
44
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibi < %s \
55
# RUN: | llvm-objdump --mattr=+experimental-xqcibi -M no-aliases -d - \
6-
# RUN: | FileCheck -check-prefix=CHECK-OBJ %s
6+
# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
77
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibi -show-encoding \
8-
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
8+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
99
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibi < %s \
1010
# RUN: | llvm-objdump --mattr=+experimental-xqcibi -d - \
1111
# RUN: | FileCheck -check-prefix=CHECK-OBJ %s
@@ -40,10 +40,10 @@ qc.bgeui x12, 11, 128
4040
# CHECK-ENC: encoding: [0x7b,0x6d,0x71,0x28]
4141
qc.bltui x2, 7, 666
4242

43-
# CHECK-INST: qc.e.beqi ra, 1, 2
44-
# CHECK-OBJ: qc.e.beqi ra, 0x1, 0x1a
45-
# CHECK-ENC: encoding: [0x1f,0xc1,0x80,0x01,0x01,0x00]
46-
qc.e.beqi x1, 1, 2
43+
# CHECK-INST: qc.e.beqi ra, 111, 2
44+
# CHECK-OBJ: qc.e.beqi ra, 0x6f, 0x1a
45+
# CHECK-ENC: encoding: [0x1f,0xc1,0x80,0x01,0x6f,0x00]
46+
qc.e.beqi x1, 111, 2
4747

4848
# CHECK-INST: qc.e.bnei tp, 115, 4094
4949
# CHECK-OBJ: qc.e.bnei tp, 0x73, 0x101c
@@ -65,7 +65,45 @@ qc.e.blti x1, 32767, 2000
6565
# CHECK-ENC: encoding: [0x1f,0x40,0xf6,0x09,0xc7,0x02]
6666
qc.e.bgeui x12, 711, 128
6767

68-
# CHECK-INST: qc.e.bltui sp, 7, 666
69-
# CHECK-OBJ: qc.e.bltui sp, 0x7, 0x2d0
70-
# CHECK-ENC: encoding: [0x1f,0x4d,0xe1,0x29,0x07,0x00]
71-
qc.e.bltui x2, 7, 666
68+
# CHECK-INST: qc.e.bltui sp, 77, 666
69+
# CHECK-OBJ: qc.e.bltui sp, 0x4d, 0x2d0
70+
# CHECK-ENC: encoding: [0x1f,0x4d,0xe1,0x29,0x4d,0x00]
71+
qc.e.bltui x2, 77, 666
72+
73+
# Check that compress patterns work as expected
74+
75+
# CHECK-NOALIAS: beqi ra, 11, 2
76+
# CHECK-ALIAS: qc.beqi ra, 11, 2
77+
# CHECK-OBJ: qc.beqi ra, 0xb, 0x3e
78+
# CHECK-ENC: encoding: [0x7b,0x81,0xb0,0x00]
79+
qc.e.beqi x1, 11, 2
80+
81+
# CHECK-NOALIAS: bnei ra, 11, 2
82+
# CHECK-ALIAS: qc.bnei ra, 11, 2
83+
# CHECK-OBJ: qc.bnei ra, 0xb, 0x42
84+
# CHECK-ENC: encoding: [0x7b,0x91,0xb0,0x00]
85+
qc.e.bnei x1, 11, 2
86+
87+
# CHECK-NOALIAS: bgei ra, 11, 2
88+
# CHECK-ALIAS: qc.bgei ra, 11, 2
89+
# CHECK-OBJ: qc.bgei ra, 0xb, 0x46
90+
# CHECK-ENC: encoding: [0x7b,0xd1,0xb0,0x00]
91+
qc.e.bgei x1, 11, 2
92+
93+
# CHECK-NOALIAS: blti ra, 11, 2
94+
# CHECK-ALIAS: qc.blti ra, 11, 2
95+
# CHECK-OBJ: qc.blti ra, 0xb, 0x4a
96+
# CHECK-ENC: encoding: [0x7b,0xc1,0xb0,0x00]
97+
qc.e.blti x1, 11, 2
98+
99+
# CHECK-NOALIAS: bgeui ra, 11, 2
100+
# CHECK-ALIAS: qc.bgeui ra, 11, 2
101+
# CHECK-OBJ: qc.bgeui ra, 0xb, 0x4e
102+
# CHECK-ENC: encoding: [0x7b,0xf1,0xb0,0x00]
103+
qc.e.bgeui x1, 11, 2
104+
105+
# CHECK-NOALIAS: bltui ra, 11, 2
106+
# CHECK-ALIAS: qc.bltui ra, 11, 2
107+
# CHECK-OBJ: qc.bltui ra, 0xb, 0x52
108+
# CHECK-ENC: encoding: [0x7b,0xe1,0xb0,0x00]
109+
qc.e.bltui x1, 11, 2

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