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2 parents f5b871b + f2f916c commit 36a8ae5Copy full SHA for 36a8ae5
Formula/y/yosys.rb
@@ -1,10 +1,8 @@
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class Yosys < Formula
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desc "Framework for Verilog RTL synthesis"
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homepage "https://yosyshq.net/yosys/"
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- # pull from git tag to get submodules
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- url "https://github.com/YosysHQ/yosys.git",
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- tag: "0.47",
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- revision: "647d61dd9212365a3cd44db219660b8f90b95cbd"
+ url "https://github.com/YosysHQ/yosys/releases/download/0.47/yosys.tar.gz"
+ sha256 "76038d3de2768567007e7c31995b17c888c16da1cf571d8a24b4c524d3eddfdf"
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license "ISC"
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revision 1
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head "https://github.com/YosysHQ/yosys.git", branch: "main"
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