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Instructions to run ACE on P550 (#86)
* prepare information how to run ACE on P550 * update README --------- Signed-off-by: Wojciech Ozga <[email protected]>
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‎README.md‎

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ACE-RISCV is an open-source project, whose goal is to deliver a confidential computing framework with a formally proven security monitor. It is based on the [canonical architecture](https://dl.acm.org/doi/pdf/10.1145/3623652.3623668) and targets RISC-V with the goal of being portable to other architectures. The formal verification efforts focus on the [security monitor implementation](security-monitor/). We invite collaborators to work with us to push the boundaries of provable confidential computing technology.
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**Formal verification:**
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This project implements the RISC-V CoVE spec's deployment model 3 referenced in [Appendix D](https://github.com/riscv-non-isa/riscv-ap-tee/blob/main/). The formal specification is embedded in the security monitor's source code and the proofs are in the [verification/](verification/) folder. Please read our [paper](https://dl.acm.org/doi/pdf/10.1145/3623652.3623668) to learn about the approach and goals.
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**Post-Quantum Cryptography (PQC) and Attestation**: ACE supports local attestation, a mechanism to authenticate confidential VMs intended for embedded systems with limited or no network connectivity. We already support PQC, specifically we use ML-KEM, SHA-384, and AES-GCM-256 cryptography.
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## Hardware requirements
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We are currently building on RISC-V 64-bit with integer (I), atomic (A) and hypervisor extentions (H), physical memory protection (PMP), memory management unit (MMU), IOPMP, core-local interrupt controller (CLINT), and supervisor timecmp extension (Sstc).
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**Real RISC-V hardware to run ACE:**
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* SiFive P550 evaluation board, [see instructions](security-monitor/platform/p550).
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## Quick Start
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Follow instructions to run one of the sample [confidential workloads](confidential-vms) under an [untrusted Linux KVM hypervisor](hypervisor/) in an emulated RISC-V environment.
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‎security-monitor/platform/p550/README.md‎

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# Supported hardware
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## SiFive P550 evaluation board
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This RISC-V processor is not compliant with the RISC-V CoVE specification because (1) it implements a pre-ratified version of the H extension, and (2) it does not support the Sstc extension. However, we have developed a version of ACE that emulates these missing hardware features. As a result, we are able to experimentally run ACE on the SiFive P550.
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Below process is not well integrated with YOCTO and requires manual execution of certain steps. We welcome pull requests to provide YOCTO integration.
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### Build SiFive p550 firmware
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We begin by building the SiFive firmware without any modifications. We use version `2024.09.00-HFP550`, as it was the version available at the time we worked with the P550 evaluation board.
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```
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export YOCTO_DIR=/tmp/yocto
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mkdir -p $YOCTO_DIR && cd $YOCTO_DIR
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git clone https://github.com/sifive/freedom-u-sdk.git -b 2024.09.00-HFP550
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BB_NUMBER_THREADS="192" PARALLEL_MAKE="-j 192" kas build $YOCTO_DIR/freedom-u-sdk/scripts/kas/hifive-premier-p550.yml
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```
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At this point, we have built the original SiFive P550 firmware. We will need the same compiler that built SiFive firmware to build ACE components.
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### Build ACE security monitor
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Let's build now the ACE security monitor. Make sure that we have access to the same compiler that yocto used to compile OpenSBI firmware.
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```
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YOCTO_RISCV_GNU_TOOLCHAIN_DIR=$YOCTO_DIR/build/tmp/work/riscv64-freedomusdk-linux/opensbi-sifive-hf-prem/1.4/recipe-sysroot-native/usr/bin/riscv64-freedomusdk-linux/
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YOCTO_CROSS_COMPILE=riscv64-freedomusdk-linux-
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ls -lah $YOCTO_RISCV_GNU_TOOLCHAIN_DIR/${YOCTO_CROSS_COMPILE}gcc
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# If you have problems with getting above compiler, you might try to force yocto to build just OpenSBI using `devtool` from poky:
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# $POKY_DIR/layers/build/scripts/devtool --basepath=$YOCTO_DIR/build build opensbi-sifive-hf-prem
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```
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Let's download ACE sources dedicated for SiFive P550.
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```
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export ACE_SRC=/tmp/ace
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export ACE_DIR=$ACE_SRC/build/
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git clone --recurse-submodules -b sifive_p550 [email protected]:IBM/ACE-RISCV.git $ACE_SRC
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```
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Build the version of the ACE security monitor dedicated for P550.
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```
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RISCV_GNU_TOOLCHAIN_WORK_DIR=$YOCTO_RISCV_GNU_TOOLCHAIN_DIR CROSS_COMPILE=$YOCTO_CROSS_COMPILE make -j192 -C $ACE_SRC security_monitor
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```
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Check presentence of the static library (`libace.a`) that contains the ACE security monitor.
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```
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ls -lah $ACE_DIR/security-monitor/libace.a
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```
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### Build OpenSBI linked with the ACE security monitor
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Let's patch SiFive's firmware. We will build OpenSBI version that is linked with the ACE security monitor and QEMU patches with support to run confidential VMs.
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```
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cd $YOCTO_DIR/meta-sifive
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git apply $ACE_SRC/security-monitor/platform/p550/patches/meta-sifive/ace.patch
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cd $YOCTO_DIR/openembedded-core
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git apply /home/woz/ace/security-monitor/platform/p550/patches/openembedded-core/qemu_ace.patch
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```
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Now its time to build the patched firmware again. Yocto will rebuilt only the components we patched, so the build process will be much faster than the initial build.
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```
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BB_NUMBER_THREADS="192" PARALLEL_MAKE="-j 192" kas build $YOCTO_DIR/freedom-u-sdk/scripts/kas/hifive-premier-p550.yml
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```
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Check that the firmware has been built.
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```
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ls -lah $YOCTO_DIR/build/tmp/deploy/images/hifive-premier-p550/bootloader_ddr5_secboot.bin
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```
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Now you can flash the new version of firmware following the standard procedure described by SiFive on its website.
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### Build host Linux kernel
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```
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cd $ACE_SRC
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RISCV_GNU_TOOLCHAIN_WORK_DIR=$YOCTO_RISCV_GNU_TOOLCHAIN_DIR CROSS_COMPILE=$YOCTO_CROSS_COMPILE make -j192 hypervisor
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```
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Check that the host Linux kernel image was built:
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```
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ls -lah $ACE_DIR/hypervisor/buildroot/build/linux-6.6.21/arch/riscv/boot/Image.gz
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```
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You can copy `Image.gz` to P550 with `scp` and then copy it to the /boot folder and reboot the system.
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```
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scp $ACE_DIR/hypervisor/buildroot/build/linux-6.6.21/arch/riscv/boot/Image.gz login@ip_of_p550:/tmp
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# you must adjust below command so that you copy to the location of the boot drive:
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sudo cp /tmp/Image.gz /run/media/boot-mmcblk0p1/Image.gz
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```
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Once you start your evaluation board with firmware containing ACE and host Linux kernel contianing CoVE patches, you should see that KVM printed the following line to dmesg:
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```
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dmesg | grep TSM
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# expected output:
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# [ 1.126289] kvm [1]: TSM version 9 is loaded and ready to run
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```
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### Build a test confidential VM
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```
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cd $ACE_SRC
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make -j192 confidential_vms
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```
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Check that the VM image was built:
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```
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ls -lah $ACE_DIR/confidential_vms/linux_vm/buildroot/images/*
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# The following files should be present
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# Image - contains guest Linux kernel
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# rootfs.ext4 - root filesystem
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# cove_tap_qemu - TVM attestation payload (for local attestation)
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```
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Now, use the `scp` tool to copy the VM image files to your P550 evaluation board.
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```
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scp $ACE_DIR/confidential_vms/linux_vm/buildroot/images/* login@ip_of_p550:/tmp
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```
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Now, run the test confidential VM on P550:
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```
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KERNEL=/tmp/Image
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DRIVE=/tmp/rootfs.ext4
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TAP=/tmp/cove_tap_qemu
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SMP=1
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MEMORY=1G
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HOST_PORT=10101
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qemu-system-riscv64 --enable-kvm -nographic \
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-machine virt,cove=true,cove-tap-filename=${TAP} -cpu rv64,sstc=false,f=true -smp ${SMP} -m ${MEMORY} \
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-kernel ${KERNEL} \
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-global virtio-mmio.force-legacy=false \
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-append "ro root=/dev/vda swiotlb=mmnn,force" \
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-device virtio-blk-pci,drive=hd0,iommu_platform=on,disable-legacy=on,disable-modern=off \
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-drive if=none,format=raw,file=${DRIVE},id=hd0 \
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-device virtio-net-pci,netdev=net0,iommu_platform=on,disable-legacy=on,disable-modern=off \
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-netdev user,id=net0,net=192.168.100.1/24,dhcpstart=192.168.100.128,hostfwd=tcp::${HOST_PORT}-:22
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```
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After a few seconds, you should see the login prompt to your confidential VM. Congratulations!
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```
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# credentials to test confidential VM
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login: root
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password: passwd
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```

‎security-monitor/platform/p550/patches/meta-sifive/ace.patch‎

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diff --git a/recipes-bsp/opensbi/opensbi-sifive-hf-prem/0009-ace.patch b/recipes-bsp/opensbi/opensbi-sifive-hf-prem/0009-ace.patch
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new file mode 100644
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index 0000000..77f2315
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--- /dev/null
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+++ b/recipes-bsp/opensbi/opensbi-sifive-hf-prem/0009-ace.patch
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@@ -0,0 +1,149 @@
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+
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+
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+
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+
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+diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
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+index 06c60ae..3582e74 100644
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+--- a/lib/sbi/sbi_domain.c
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++++ b/lib/sbi/sbi_domain.c
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+@@ -796,16 +796,16 @@ int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid)
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+ root.possible_harts = root_hmask;
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+
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+ /* Root domain firmware memory region */
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+- sbi_domain_memregion_init(scratch->fw_start, scratch->fw_rw_offset,
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+- (SBI_DOMAIN_MEMREGION_M_READABLE |
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++ sbi_domain_memregion_init(scratch->fw_start, scratch->fw_size,
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++ (SBI_DOMAIN_MEMREGION_M_READABLE | SBI_DOMAIN_MEMREGION_M_WRITABLE |
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+ SBI_DOMAIN_MEMREGION_M_EXECUTABLE),
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+ &root_memregs[root_memregs_count++],0);
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+
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+- sbi_domain_memregion_init((scratch->fw_start + scratch->fw_rw_offset),
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+- (scratch->fw_size - scratch->fw_rw_offset),
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+- (SBI_DOMAIN_MEMREGION_M_READABLE |
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+- SBI_DOMAIN_MEMREGION_M_WRITABLE),
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+- &root_memregs[root_memregs_count++],0);
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++ // sbi_domain_memregion_init((scratch->fw_start + scratch->fw_rw_offset),
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++ // (scratch->fw_size - scratch->fw_rw_offset),
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++ // (SBI_DOMAIN_MEMREGION_M_READABLE |
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++ // SBI_DOMAIN_MEMREGION_M_WRITABLE),
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++ // &root_memregs[root_memregs_count++],0);
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+
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+ #ifdef CONFIG_PLATFORM_ESWIN
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+ sbi_domain_memregion_init(0x1000000000UL, 0x3fffffUL, SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS,
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+diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
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+index f621cdd..68b2b18 100644
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+--- a/lib/sbi/sbi_hart.c
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++++ b/lib/sbi/sbi_hart.c
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+@@ -435,7 +435,7 @@ static int sbi_hart_smepmp_configure(struct sbi_scratch *scratch,
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+ pmp_disable(SBI_SMEPMP_RESV_ENTRY);
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+
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+ /* Program M-only regions when MML is not set. */
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+- pmp_idx = 0;
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++ pmp_idx = 2;
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+ sbi_domain_for_each_memregion(dom, reg) {
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+ /* Skip reserved entry */
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+ if (pmp_idx == SBI_SMEPMP_RESV_ENTRY)
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+@@ -461,7 +461,7 @@ static int sbi_hart_smepmp_configure(struct sbi_scratch *scratch,
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+ csr_set(CSR_MSECCFG, MSECCFG_MML);
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+
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+ /* Program shared and SU-only regions */
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+- pmp_idx = 0;
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++ pmp_idx = 2;
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+ sbi_domain_for_each_memregion(dom, reg) {
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+ /* Skip reserved entry */
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+ if (pmp_idx == SBI_SMEPMP_RESV_ENTRY)
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+@@ -498,7 +498,7 @@ static int sbi_hart_oldpmp_configure(struct sbi_scratch *scratch,
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+ {
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+ struct sbi_domain_memregion *reg;
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+ struct sbi_domain *dom = sbi_domain_thishart_ptr();
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+- unsigned int pmp_idx = 0;
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++ unsigned int pmp_idx = 2;
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+ unsigned int pmp_flags;
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+ unsigned long pmp_addr;
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+
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+diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c
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+index 3d60ceb..3870971 100644
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+--- a/lib/sbi/sbi_hsm.c
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++++ b/lib/sbi/sbi_hsm.c
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+@@ -26,6 +26,8 @@
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+ #include <sbi/sbi_timer.h>
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+ #include <sbi/sbi_console.h>
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+
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++extern void ace_setup_this_hart();
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++
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+ #define __sbi_hsm_hart_change_state(hdata, oldstate, newstate) \
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+ ({ \
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+ long state = atomic_cmpxchg(&(hdata)->state, oldstate, newstate); \
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+@@ -154,6 +156,8 @@ void __noreturn sbi_hsm_hart_start_finish(struct sbi_scratch *scratch,
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+ next_mode = scratch->next_mode;
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+ hsm_start_ticket_release(hdata);
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+
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++ ace_setup_this_hart();
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++
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+ sbi_hart_switch_mode(hartid, next_arg1, next_addr, next_mode, false);
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+ }
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+
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+diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
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+index 931ba7c..9c0454b 100644
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+--- a/lib/sbi/sbi_init.c
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++++ b/lib/sbi/sbi_init.c
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+@@ -80,6 +80,8 @@ static void sbi_boot_print_general(struct sbi_scratch *scratch)
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+ return;
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+
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+ /* Platform details */
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++ sbi_printf("ACE: 2024.09.00-HFP550 release\n");
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++ sbi_printf("ACE: build version %d\n", 152);
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+ sbi_printf("Platform Name : %s\n",
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+ sbi_platform_name(plat));
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+ sbi_platform_get_features_str(plat, str, sizeof(str));
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+diff --git a/lib/utils/serial/uart8250.c b/lib/utils/serial/uart8250.c
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+index 1fe053f..af114dd 100644
107+
+--- a/lib/utils/serial/uart8250.c
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++++ b/lib/utils/serial/uart8250.c
109+
+@@ -135,7 +135,12 @@ int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
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+
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+ sbi_console_set_device(&uart8250_console);
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+
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++#ifdef CONFIG_PLATFORM_ESWIN
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++ /* For now, not adding memrange for UART as we are short of PMP regions */
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++ return 0;
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++#else
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+ return sbi_domain_root_add_memrange(base, PAGE_SIZE, PAGE_SIZE,
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+ (SBI_DOMAIN_MEMREGION_MMIO |
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+ SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));
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++#endif
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+ }
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+diff --git a/platform/eswin/eic770x/objects.mk b/platform/eswin/eic770x/objects.mk
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+index 8535107..7d6806d 100644
124+
+--- a/platform/eswin/eic770x/objects.mk
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++++ b/platform/eswin/eic770x/objects.mk
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+@@ -15,7 +15,7 @@ platform-objs-y += eic770x_uart.o
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+ platform-cppflags-y =
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+ platform-cflags-y =
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+ platform-asflags-y =
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+-platform-ldflags-y = -fno-stack-protector
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++platform-ldflags-y = -fno-stack-protector -L/opt/woz/ace_p550/security-monitor/ -lace
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+
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+ # Command for platform specific "make run"
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+
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+diff --git a/platform/eswin/eic770x/platform.c b/platform/eswin/eic770x/platform.c
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+index e15df16..cbf581a 100644
137+
+--- a/platform/eswin/eic770x/platform.c
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++++ b/platform/eswin/eic770x/platform.c
139+
+@@ -30,6 +30,8 @@
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+ #include <sbi/sbi_hart.h>
141+
+ #include "eic770x_uart.h"
142+
+
143+
++extern void init_security_monitor_asm(bool cold_boot, void *fdt);
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++
145+
+ /* clang-format off */
146+
+ #define EIC770X_HART_COUNT 4
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+ #define DIE_REG_OFFSET 0
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+@@ -225,6 +227,7 @@ static int eic770x_final_init(bool cold_boot)
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+
150+
+ fdt = sbi_scratch_thishart_arg1_ptr();
151+
+ eic770x_modify_dt(fdt);
152+
++ init_security_monitor_asm(cold_boot, fdt);
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+
154+
+ return 0;
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+ }
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diff --git a/recipes-bsp/opensbi/opensbi-sifive-hf-prem_1.4.bb b/recipes-bsp/opensbi/opensbi-sifive-hf-prem_1.4.bb
157+
index 4a7bf4b..8740670 100644
158+
--- a/recipes-bsp/opensbi/opensbi-sifive-hf-prem_1.4.bb
159+
+++ b/recipes-bsp/opensbi/opensbi-sifive-hf-prem_1.4.bb
160+
@@ -21,13 +21,15 @@ SRC_URI:append = " \
161+
file://0005-lib-sbi-Configure-CSR-registers.patch \
162+
file://0006-lib-sbi-eic770x-Add-PMP-for-TOR-region.patch \
163+
file://0007-sbi-init-Modify-CSR-values.patch \
164+
+ file://0009-ace.patch \
165+
"
166+
167+
S = "${WORKDIR}/git"
168+
169+
TARGET_CC_ARCH += "${LDFLAGS}"
170+
171+
-EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} CHIPLET="BR2_CHIPLET_1" CHIPLET_DIE_AVAILABLE="BR2_CHIPLET_1_DIE0_AVAILABLE" MEM_MODE="BR2_MEMMODE_FLAT" PLATFORM_CLUSTER_X_CORE="BR2_CLUSTER_4_CORE" PLATFORM_RISCV_ISA=rv64imafdc_zicsr_zifencei I=${D}"
172+
+
173+
+EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} CHIPLET="BR2_CHIPLET_1" CHIPLET_DIE_AVAILABLE="BR2_CHIPLET_1_DIE0_AVAILABLE" MEM_MODE="BR2_MEMMODE_FLAT" PLATFORM_CLUSTER_X_CORE="BR2_CLUSTER_4_CORE" PLATFORM_RISCV_ISA=rv64imafdc_zicsr_zifencei PLATFORM_RISCV_ABI=lp64d I=${D}"
174+
# If RISCV_SBI_PAYLOAD is set then include it as a payload
175+
EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_image(d)}"
176+
EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_fdt(d)}"
177+
diff --git a/recipes-bsp/u-boot/files/0002-ace-p550.patch b/recipes-bsp/u-boot/files/0002-ace-p550.patch
178+
new file mode 100644
179+
index 0000000..407d46f
180+
--- /dev/null
181+
+++ b/recipes-bsp/u-boot/files/0002-ace-p550.patch
182+
@@ -0,0 +1,13 @@
183+
+diff --git a/arch/riscv/cpu/eic7700/dram.c b/arch/riscv/cpu/eic7700/dram.c
184+
+index a3521ac1e4..0728819cc2 100644
185+
+--- a/arch/riscv/cpu/eic7700/dram.c
186+
++++ b/arch/riscv/cpu/eic7700/dram.c
187+
+@@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
188+
+ DECLARE_GLOBAL_DATA_PTR;
189+
+
190+
+ /* 32 GB */
191+
+-#define DDR_SIZE_MAX 0x800000000
192+
++#define DDR_SIZE_MAX 0x200000000
193+
+
194+
+ /* 128 MB offset */
195+
+ #define RAM_BASE_OFFSET 0x8000000
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diff --git a/recipes-bsp/u-boot/u-boot-sifive-hf-prem_2024.01.bb b/recipes-bsp/u-boot/u-boot-sifive-hf-prem_2024.01.bb
197+
index 1887c67..55a9357 100644
198+
--- a/recipes-bsp/u-boot/u-boot-sifive-hf-prem_2024.01.bb
199+
+++ b/recipes-bsp/u-boot/u-boot-sifive-hf-prem_2024.01.bb
200+
@@ -7,10 +7,16 @@ DEPENDS += "bc-native dtc-native"
201+
202+
SRCREV = "419a5fb2a92d338e813771acb0b50fefd9a1fea0"
203+
SRC_URI = "git://github.com/eswincomputing/u-boot.git;protocol=https;branch=u-boot-2024.01-EIC7X \
204+
- file://0001-riscv-hifive_premier_p550-defined-boot-media-sequenc.patch"
205+
+ file://0001-riscv-hifive_premier_p550-defined-boot-media-sequenc.patch \
206+
+ file://0002-ace-p550.patch \
207+
+ "
208+
209+
do_deploy:append () {
210+
install -m 755 ${B}/u-boot.dtb ${DEPLOYDIR}
211+
+ cp ${DEPLOYDIR}/u-boot.dtb ${DEPLOYDIR}/u-boot_original.dtb
212+
+ fdtput -c ${DEPLOYDIR}/u-boot.dtb /reserved-memory/ace-conf-mem
213+
+ fdtput -t x ${DEPLOYDIR}/u-boot.dtb /reserved-memory/ace-conf-mem reg 0x2 0x80000000 0x2 0x0
214+
+ fdtput -t s ${DEPLOYDIR}/u-boot.dtb /reserved-memory/ace-conf-mem no-map
215+
}
216+
217+
COMPATIBLE_MACHINE = "hifive-premier-p550"

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