Question about padring and package

[mole99]

Hello! I have a few questions regarding the IP selection:

3. The maximum area below 2 mm2 preferred (larger designs only if area is available)

Which means we can create a custom padring with >2mm2 if we need more space and area is available?
How does this work with dicing the wafer if some chips have a different geometry?
Up to how many I/Os can we use? What package is used for the chips? Or won't the chips be packaged at all?

Thanks!