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Description
Hello all,
First of all, this is an awesome project! I've done something similar for another cheap chinese chip (PHY6222) so I know the hurdles of navigating through poorly supported SDKs and chips.
In any case, I have multiple boards of walkie talkies from Baofeng, which have one of the PY32F002AF15P6TU, and an integrated walkie talkie chip. No documentation on said chip is available online (AT1141). I've traced the footprint to be similar to the RDA1846 (at least the power lines, i2c lines, etc).
However, doing a quick I2C logic dump reveals that it's indeed NOT a RDA1846 (even if it uses the same address!). In any case, I'm tracing the connections from all the chips on the board to the Puya MCU; I already have maped that the I2C lines are connected to PA0 and PA1 (which is weird since this MCU doesn't have I2C as an alternative functionality of these pads, but whatever).
There are the SWD pins exposed on the backside of the board, but I've figured that either the MCU re-purposes those pins for something else, and/or the NRST is also used for something different than reset. I've verified that pulling NRST low and powering up the board makes it to not do absolutely anything; but once it "starts", pulling NRST low doesn't reset or holds the processor in reset.
In any case, I'm using a J-Link ARM probe, I've tried the J-Flash with the JLinkDevices + jlink-script, and openocd with a custom config file (stolen from the stm32f0x, which I don't know which DAP tap id to use, so that's mostly what I wanted to ask here your thoughts); but nothing works. There's no reply from the device, and I suspect it's because they're using the SWDIO and SWDCLK pins for something else. Even if I connect the NRST pin to the J-Link probe, it can't reset it (as I've mentioned above).
In any case, the cfg file for openocd contains this (even if it's not working):
# SPDX-License-Identifier: GPL-2.0-or-later
# script for py32f02 family
#
# stm32 devices support SWD transports only.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME py32f02
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0xC00
}
# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
set _FLASH_SIZE $FLASH_SIZE
} else {
# autodetect size
set _FLASH_SIZE 0x5000
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0bb11477 # this is not right
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
#######flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter speed 1000
adapter srst delay 100
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
# Default hooks
#######$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
#######$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
#######$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }
I'm NOT changing the BOOT0 pin at all, it's held with its default value from the original circuit (which I think it's pulling it low? can't trace where it's connected though)
I'd appreciate any feedback you can give!
Thanks.