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ChunyuLiaoIanWood1
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IanWood1
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[RISCV] Add smcntrpmf extension (llvm#136556)
spec: https://github.com/riscvarchive/riscv-smcntrpmf
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -123,6 +123,7 @@
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// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
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// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
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// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
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// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)
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// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
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// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
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// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)

‎clang/test/Preprocessor/riscv-target-features.c‎

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// CHECK-NOT: __riscv_shvstvecd {{.*$}}
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// CHECK-NOT: __riscv_smaia {{.*$}}
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// CHECK-NOT: __riscv_smcdeleg {{.*$}}
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// CHECK-NOT: __riscv_smcntrpmf {{.*$}}
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// CHECK-NOT: __riscv_smcsrind {{.*$}}
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// CHECK-NOT: __riscv_smdbltrp {{.*$}}
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// CHECK-NOT: __riscv_smepmp {{.*$}}
@@ -1445,6 +1446,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
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// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismcntrpmf1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64ismcntrpmf1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
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// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismcsrind1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -128,6 +128,7 @@ on support follow.
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``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Smaia`` Supported
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``Smcdeleg`` Supported
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``Smcntrpmf`` Supported
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``Smcsrind`` Supported
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``Smdbltrp`` Supported
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``Smepmp`` Supported

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -899,6 +899,9 @@ def FeatureStdExtSsaia
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: RISCVExtension<1, 0,
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"Advanced Interrupt Architecture Supervisor Level">;
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def FeatureStdExtSmcntrpmf
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: RISCVExtension<1, 0, "Cycle and Instret Privilege Mode Filtering">;
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def FeatureStdExtSmcsrind
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: RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;
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def FeatureStdExtSscsrind

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td‎

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@@ -482,6 +482,16 @@ def : SysReg<"sctrdepth", 0x15f>;
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def : SysReg<"vsctrctl", 0x24e>;
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def : SysReg<"mctrctl", 0x34e>;
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//===-----------------------------------------------
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// Cycle and Instret Privilege Mode Filtering (Smcntrpmf)
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//===-----------------------------------------------
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def : SysReg<"mcyclecfg", 0x321>;
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def : SysReg<"minstretcfg", 0x322>;
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let isRV32Only = 1 in {
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def : SysReg<"mcyclecfgh", 0x721>;
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def : SysReg<"minstretcfgh", 0x722>;
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} // isRV32Only
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//===-----------------------------------------------
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// Vendor CSRs
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//===-----------------------------------------------

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -147,6 +147,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s
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; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
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; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -301,6 +302,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s
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; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
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; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -485,6 +487,7 @@
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; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
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; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
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; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
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; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
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; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
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; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
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; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -636,6 +639,7 @@
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; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
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; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
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; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
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; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
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; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
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; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
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; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"

‎llvm/test/CodeGen/RISCV/features-info.ll‎

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; CHECK-NEXT: sifive7 - SiFive 7-Series processors.
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; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level).
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; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
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; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).
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; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
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; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
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; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).

‎llvm/test/MC/RISCV/attribute-arch.s‎

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.attribute arch, "rv32i_smcdeleg1p0"
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# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
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.attribute arch, "rv32i_smcntrpmf1p0"
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# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0"
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.attribute arch, "rv32i_smepmp1p0"
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# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
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‎llvm/test/MC/RISCV/machine-csr-names.s‎

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@@ -2733,3 +2733,27 @@ csrrs t2, 0x742, zero
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csrrs t1, mnstatus, zero
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# uimm12
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csrrs t2, 0x744, zero
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# mcyclecfg
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# name
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# CHECK-INST: csrrs t1, mcyclecfg, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x32]
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# CHECK-INST-ALIAS: csrr t1, mcyclecfg
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csrrs t1, mcyclecfg, zero
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# uimm12
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# CHECK-INST: csrrs t2, mcyclecfg, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x32]
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# CHECK-INST-ALIAS: csrr t2, mcyclecfg
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csrrs t2, 0x321, zero
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# minstretcfg
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# name
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# CHECK-INST: csrrs t1, minstretcfg, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0x32]
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# CHECK-INST-ALIAS: csrr t1, minstretcfg
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csrrs t1, minstretcfg, zero
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# uimm12
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# CHECK-INST: csrrs t2, minstretcfg, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x32]
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# CHECK-INST-ALIAS: csrr t2, minstretcfg
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csrrs t2, 0x322, zero

‎llvm/test/MC/RISCV/rv32-machine-csr-names.s‎

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@@ -1163,3 +1163,27 @@ csrrs t2, 0x319, zero
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csrrs t1, miph, zero
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# uimm12
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csrrs t2, 0x354, zero
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# mcyclecfgh
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# name
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# CHECK-INST: csrrs t1, mcyclecfgh, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x72]
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# CHECK-INST-ALIAS: csrr t1, mcyclecfgh
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csrrs t1, mcyclecfgh, zero
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# uimm12
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# CHECK-INST: csrrs t2, mcyclecfgh, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x72]
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# CHECK-INST-ALIAS: csrr t2, mcyclecfgh
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csrrs t2, 0x721, zero
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# minstretcfgh
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# name
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# CHECK-INST: csrrs t1, minstretcfgh, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0x72]
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# CHECK-INST-ALIAS: csrr t1, minstretcfgh
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csrrs t1, minstretcfgh, zero
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# uimm12
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# CHECK-INST: csrrs t2, minstretcfgh, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x72]
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# CHECK-INST-ALIAS: csrr t2, minstretcfgh
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csrrs t2, 0x722, zero

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