Sparc: Remove fixup kinds for WDISP16/WDISP19/WDISP22

Similar to f39696e

Author: MaskRay

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

@@ -35,13 +35,13 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
   case Sparc::fixup_sparc_call30:
     return (Value >> 2) & 0x3fffffff;
 
-  case Sparc::fixup_sparc_br22:
+  case ELF::R_SPARC_WDISP22:
     return (Value >> 2) & 0x3fffff;
 
-  case Sparc::fixup_sparc_br19:
+  case ELF::R_SPARC_WDISP19:
     return (Value >> 2) & 0x7ffff;
 
-  case Sparc::fixup_sparc_br16: {
+  case ELF::R_SPARC_WDISP16: {
     // A.3 Branch on Integer Register with Prediction (BPr)
     // Inst{21-20} = d16hi;
     // Inst{13-0}  = d16lo;
@@ -127,9 +127,6 @@ namespace {
       const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br16",       0,     32,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_13",        19,     13,  0 },
         { "fixup_sparc_hi22",      10,     22,  0 },
         { "fixup_sparc_lo10",      22,     10,  0 },
@@ -143,9 +140,6 @@ namespace {
       const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     0,     30,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br16",      32,      0,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_13",         0,     13,  0 },
         { "fixup_sparc_hi22",       0,     22,  0 },
         { "fixup_sparc_lo10",       0,     10,  0 },
@@ -177,6 +171,15 @@ namespace {
       case ELF::R_SPARC_PC22:
         Info = {"", 10, 22, MCFixupKindInfo::FKF_IsPCRel};
         break;
+      case ELF::R_SPARC_WDISP16:
+        Info = {"", 0, 32, MCFixupKindInfo::FKF_IsPCRel};
+        break;
+      case ELF::R_SPARC_WDISP19:
+        Info = {"", 13, 19, MCFixupKindInfo::FKF_IsPCRel};
+        break;
+      case ELF::R_SPARC_WDISP22:
+        Info = {"", 10, 22, MCFixupKindInfo::FKF_IsPCRel};
+        break;
       }
       if (Endian == llvm::endianness::little)
         Info.TargetOffset = 32 - Info.TargetOffset - Info.TargetSize;

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

@@ -91,10 +91,6 @@ unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
       if (Ctx.getObjectFileInfo()->isPositionIndependent())
         return ELF::R_SPARC_WPLT30;
       return ELF::R_SPARC_WDISP30;
-    case Sparc::fixup_sparc_br22:    return ELF::R_SPARC_WDISP22;
-    case Sparc::fixup_sparc_br19:    return ELF::R_SPARC_WDISP19;
-    case Sparc::fixup_sparc_br16:
-      return ELF::R_SPARC_WDISP16;
     }
   }
 

llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h

@@ -18,17 +18,6 @@ namespace llvm {
       // fixup_sparc_call30 - 30-bit PC relative relocation for call
       fixup_sparc_call30 = FirstTargetFixupKind,
 
-      /// fixup_sparc_br22 - 22-bit PC relative relocation for
-      /// branches
-      fixup_sparc_br22,
-
-      /// fixup_sparc_br19 - 19-bit PC relative relocation for
-      /// branches on icc/xcc
-      fixup_sparc_br19,
-
-      /// fixup_sparc_bpr  - 16-bit fixup for bpr
-      fixup_sparc_br16,
-
       /// fixup_sparc_13 - 13-bit fixup
       fixup_sparc_13,
 

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

@@ -190,34 +190,29 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   (MCFixupKind)Sparc::fixup_sparc_br22));
+  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP22));
   return 0;
 }
 
-unsigned SparcMCCodeEmitter::
-getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
-                           SmallVectorImpl<MCFixup> &Fixups,
-                           const MCSubtargetInfo &STI) const {
+unsigned SparcMCCodeEmitter::getBranchPredTargetOpValue(
+    const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   (MCFixupKind)Sparc::fixup_sparc_br19));
+  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP19));
   return 0;
 }
 
-unsigned SparcMCCodeEmitter::
-getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
-                           SmallVectorImpl<MCFixup> &Fixups,
-                           const MCSubtargetInfo &STI) const {
+unsigned SparcMCCodeEmitter::getBranchOnRegTargetOpValue(
+    const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(
-      MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16));
+  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP16));
 
   return 0;
 }