@@ -2686,6 +2686,9 @@ InstructionCost VPWidenMemoryRecipe::computeCost(ElementCount VF,
26862686 getLoadStoreAlignment (const_cast <Instruction *>(&Ingredient));
26872687 unsigned AS = cast<PointerType>(Ctx.Types .inferScalarType (getAddr ()))
26882688 ->getAddressSpace ();
2689+ unsigned Opcode = isa<VPWidenLoadRecipe, VPWidenLoadEVLRecipe>(this )
2690+ ? Instruction::Load
2691+ : Instruction::Store;
26892692
26902693 if (!Consecutive) {
26912694 // TODO: Using the original IR may not be accurate.
@@ -2695,20 +2698,19 @@ InstructionCost VPWidenMemoryRecipe::computeCost(ElementCount VF,
26952698 assert (!Reverse &&
26962699 " Inconsecutive memory access should not have the order." );
26972700 return Ctx.TTI .getAddressComputationCost (Ty) +
2698- Ctx.TTI .getGatherScatterOpCost (Ingredient.getOpcode (), Ty, Ptr,
2699- IsMasked, Alignment, Ctx.CostKind ,
2700- &Ingredient);
2701+ Ctx.TTI .getGatherScatterOpCost (Opcode, Ty, Ptr, IsMasked, Alignment,
2702+ Ctx.CostKind , &Ingredient);
27012703 }
27022704
27032705 InstructionCost Cost = 0 ;
27042706 if (IsMasked) {
2705- Cost += Ctx. TTI . getMaskedMemoryOpCost (Ingredient. getOpcode (), Ty, Alignment,
2706- AS, Ctx.CostKind );
2707+ Cost +=
2708+ Ctx. TTI . getMaskedMemoryOpCost (Opcode, Ty, Alignment, AS, Ctx.CostKind );
27072709 } else {
27082710 TTI::OperandValueInfo OpInfo =
27092711 Ctx.TTI .getOperandInfo (Ingredient.getOperand (0 ));
2710- Cost += Ctx.TTI .getMemoryOpCost (Ingredient. getOpcode () , Ty, Alignment, AS,
2711- Ctx. CostKind , OpInfo, &Ingredient);
2712+ Cost += Ctx.TTI .getMemoryOpCost (Opcode , Ty, Alignment, AS, Ctx. CostKind ,
2713+ OpInfo, &Ingredient);
27122714 }
27132715 if (!Reverse)
27142716 return Cost;
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