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[RISCV] Simplify fixup kinds that force relocations
For RELA targets, fixup kinds that force relocations (GOT, TLS, ALIGN, RELAX, etc) can bypass `applyFixup` and be encoded as `FirstRelocationKind+i`, as seen in LoongArch. This patch removes redundant fixup kinds and adopts the `FirstRelocationKind+i` encoding. The `llvm-mc -show-encoding` output no longer displays descriptive fixup names, as this information is removed from `RISCVAsmBackend::getFixupKindInfo`. While a backend hook could be added to call `llvm::object::getELFRelocationTypeName`, it's unnecessary since the relocation in `-filetype=obj` output is what truly matters. Pull Request: llvm#136088
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7 files changed

+56
-140
lines changed

7 files changed

+56
-140
lines changed

‎llvm/lib/MC/MCAssembler.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,7 @@ bool MCAssembler::evaluateFixup(const MCFixup &Fixup, const MCFragment *DF,
203203
if (IsResolved) {
204204
auto TargetVal = Target;
205205
TargetVal.Cst = Value;
206-
if (Fixup.getKind() >= FirstLiteralRelocationKind ||
206+
if (Fixup.getKind() >= FirstRelocationKind ||
207207
getBackend().shouldForceRelocation(*this, Fixup, TargetVal, STI))
208208
IsResolved = false;
209209
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp‎

Lines changed: 19 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,14 @@ static cl::opt<bool> ULEB128Reloc(
3434
"riscv-uleb128-reloc", cl::init(true), cl::Hidden,
3535
cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"));
3636

37+
RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI,
38+
bool Is64Bit, const MCTargetOptions &Options)
39+
: MCAsmBackend(llvm::endianness::little,
40+
FirstRelocationKind + ELF::R_RISCV_RELAX),
41+
STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
42+
RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
43+
}
44+
3745
std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
3846
if (STI.getTargetTriple().isOSBinFormatELF()) {
3947
unsigned Type;
@@ -71,27 +79,13 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
7179
MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
7280
{"fixup_riscv_pcrel_lo12_s", 0, 32,
7381
MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
74-
{"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
75-
{"fixup_riscv_tprel_hi20", 12, 20, 0},
76-
{"fixup_riscv_tprel_lo12_i", 20, 12, 0},
77-
{"fixup_riscv_tprel_lo12_s", 0, 32, 0},
78-
{"fixup_riscv_tprel_add", 0, 0, 0},
79-
{"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
80-
{"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
8182
{"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
8283
{"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
8384
{"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
8485
{"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
8586
{"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
8687
{"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
87-
{"fixup_riscv_relax", 0, 0, 0},
88-
{"fixup_riscv_align", 0, 0, 0},
8988

90-
{"fixup_riscv_tlsdesc_hi20", 12, 20,
91-
MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
92-
{"fixup_riscv_tlsdesc_load_lo12", 20, 12, 0},
93-
{"fixup_riscv_tlsdesc_add_lo12", 20, 12, 0},
94-
{"fixup_riscv_tlsdesc_call", 0, 0, 0},
9589
{"fixup_riscv_qc_e_branch", 0, 48, MCFixupKindInfo::FKF_IsPCRel},
9690
{"fixup_riscv_qc_e_32", 16, 32, 0},
9791
{"fixup_riscv_qc_abs20_u", 12, 20, 0},
@@ -100,9 +94,9 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
10094
static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
10195
"Not all fixup kinds added to Infos array");
10296

103-
// Fixup kinds from .reloc directive are like R_RISCV_NONE. They
104-
// do not require any extra processing.
105-
if (Kind >= FirstLiteralRelocationKind)
97+
// Fixup kinds from raw relocation types and .reloc directive are like
98+
// R_RISCV_NONE. They do not require any extra processing.
99+
if (Kind >= FirstRelocationKind)
106100
return MCAsmBackend::getFixupKindInfo(FK_NONE);
107101

108102
if (Kind < FirstTargetFixupKind)
@@ -131,11 +125,6 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
131125
if (Target.isAbsolute())
132126
return false;
133127
break;
134-
case RISCV::fixup_riscv_got_hi20:
135-
case RISCV::fixup_riscv_tls_got_hi20:
136-
case RISCV::fixup_riscv_tls_gd_hi20:
137-
case RISCV::fixup_riscv_tlsdesc_hi20:
138-
return true;
139128
}
140129

141130
return STI->hasFeature(RISCV::FeatureRelax) || ForceRelocs;
@@ -456,11 +445,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
456445
switch (Fixup.getTargetKind()) {
457446
default:
458447
llvm_unreachable("Unknown fixup kind!");
459-
case RISCV::fixup_riscv_got_hi20:
460-
case RISCV::fixup_riscv_tls_got_hi20:
461-
case RISCV::fixup_riscv_tls_gd_hi20:
462-
case RISCV::fixup_riscv_tlsdesc_hi20:
463-
llvm_unreachable("Relocation should be unconditionally forced\n");
464448
case FK_Data_1:
465449
case FK_Data_2:
466450
case FK_Data_4:
@@ -469,8 +453,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
469453
return Value;
470454
case RISCV::fixup_riscv_lo12_i:
471455
case RISCV::fixup_riscv_pcrel_lo12_i:
472-
case RISCV::fixup_riscv_tprel_lo12_i:
473-
case RISCV::fixup_riscv_tlsdesc_load_lo12:
474456
return Value & 0xfff;
475457
case RISCV::fixup_riscv_12_i:
476458
if (!isInt<12>(Value)) {
@@ -480,11 +462,9 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
480462
return Value & 0xfff;
481463
case RISCV::fixup_riscv_lo12_s:
482464
case RISCV::fixup_riscv_pcrel_lo12_s:
483-
case RISCV::fixup_riscv_tprel_lo12_s:
484465
return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
485466
case RISCV::fixup_riscv_hi20:
486467
case RISCV::fixup_riscv_pcrel_hi20:
487-
case RISCV::fixup_riscv_tprel_hi20:
488468
// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
489469
return ((Value + 0x800) >> 12) & 0xfffff;
490470
case RISCV::fixup_riscv_jal: {
@@ -602,7 +582,6 @@ bool RISCVAsmBackend::evaluateTargetFixup(
602582
switch (Fixup.getTargetKind()) {
603583
default:
604584
llvm_unreachable("Unexpected fixup kind!");
605-
case RISCV::fixup_riscv_tlsdesc_hi20:
606585
case RISCV::fixup_riscv_pcrel_hi20:
607586
AUIPCFixup = &Fixup;
608587
AUIPCDF = DF;
@@ -642,7 +621,7 @@ bool RISCVAsmBackend::evaluateTargetFixup(
642621
Value = Asm.getSymbolOffset(SA) + AUIPCTarget.getConstant();
643622
Value -= Asm.getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset();
644623

645-
return !shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, STI);
624+
return AUIPCFixup->getTargetKind() == RISCV::fixup_riscv_pcrel_hi20;
646625
}
647626

648627
bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,
@@ -680,12 +659,10 @@ bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,
680659
}
681660
MCValue A = MCValue::get(Target.getAddSym(), nullptr, Target.getConstant());
682661
MCValue B = MCValue::get(Target.getSubSym());
683-
auto FA = MCFixup::create(
684-
Fixup.getOffset(), nullptr,
685-
static_cast<MCFixupKind>(FirstLiteralRelocationKind + TA));
686-
auto FB = MCFixup::create(
687-
Fixup.getOffset(), nullptr,
688-
static_cast<MCFixupKind>(FirstLiteralRelocationKind + TB));
662+
auto FA =
663+
MCFixup::create(Fixup.getOffset(), nullptr, FirstRelocationKind + TA);
664+
auto FB =
665+
MCFixup::create(Fixup.getOffset(), nullptr, FirstRelocationKind + TB);
689666
auto &Assembler = const_cast<MCAssembler &>(Asm);
690667
Asm.getWriter().recordRelocation(Assembler, &F, FA, A, FixedValueA);
691668
Asm.getWriter().recordRelocation(Assembler, &F, FB, B, FixedValueB);
@@ -699,7 +676,7 @@ void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
699676
bool IsResolved,
700677
const MCSubtargetInfo *STI) const {
701678
MCFixupKind Kind = Fixup.getKind();
702-
if (Kind >= FirstLiteralRelocationKind)
679+
if (Kind >= FirstRelocationKind)
703680
return;
704681
MCContext &Ctx = Asm.getContext();
705682
MCFixupKindInfo Info = getFixupKindInfo(Kind);
@@ -767,8 +744,8 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
767744
MCContext &Ctx = Asm.getContext();
768745
const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
769746
// Create fixup_riscv_align fixup.
770-
MCFixup Fixup =
771-
MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc());
747+
MCFixup Fixup = MCFixup::create(
748+
0, Dummy, FirstRelocationKind + ELF::R_RISCV_ALIGN, SMLoc());
772749

773750
uint64_t FixedValue = 0;
774751
MCValue NopBytes = MCValue::get(Count);

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -30,11 +30,7 @@ class RISCVAsmBackend : public MCAsmBackend {
3030

3131
public:
3232
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
33-
const MCTargetOptions &Options)
34-
: MCAsmBackend(llvm::endianness::little, RISCV::fixup_riscv_relax),
35-
STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
36-
RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
37-
}
33+
const MCTargetOptions &Options);
3834
~RISCVAsmBackend() override = default;
3935

4036
void setForceRelocs() { ForceRelocs = true; }

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp‎

Lines changed: 5 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
5151
const MCFixup &Fixup,
5252
bool IsPCRel) const {
5353
const MCExpr *Expr = Fixup.getValue();
54-
// Determine the type of the relocation
5554
unsigned Kind = Fixup.getTargetKind();
5655
auto Spec = RISCVMCExpr::Specifier(Target.getSpecifier());
5756
switch (Spec) {
@@ -74,6 +73,11 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
7473
break;
7574
}
7675

76+
// Extract the relocation type from the fixup kind, after applying STT_TLS as
77+
// needed.
78+
if (Kind >= FirstRelocationKind)
79+
return Kind - FirstRelocationKind;
80+
7781
if (IsPCRel) {
7882
switch (Kind) {
7983
default:
@@ -88,20 +92,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
8892
return ELF::R_RISCV_PCREL_LO12_I;
8993
case RISCV::fixup_riscv_pcrel_lo12_s:
9094
return ELF::R_RISCV_PCREL_LO12_S;
91-
case RISCV::fixup_riscv_got_hi20:
92-
return ELF::R_RISCV_GOT_HI20;
93-
case RISCV::fixup_riscv_tls_got_hi20:
94-
return ELF::R_RISCV_TLS_GOT_HI20;
95-
case RISCV::fixup_riscv_tls_gd_hi20:
96-
return ELF::R_RISCV_TLS_GD_HI20;
97-
case RISCV::fixup_riscv_tlsdesc_hi20:
98-
return ELF::R_RISCV_TLSDESC_HI20;
99-
case RISCV::fixup_riscv_tlsdesc_load_lo12:
100-
return ELF::R_RISCV_TLSDESC_LOAD_LO12;
101-
case RISCV::fixup_riscv_tlsdesc_add_lo12:
102-
return ELF::R_RISCV_TLSDESC_ADD_LO12;
103-
case RISCV::fixup_riscv_tlsdesc_call:
104-
return ELF::R_RISCV_TLSDESC_CALL;
10595
case RISCV::fixup_riscv_jal:
10696
return ELF::R_RISCV_JAL;
10797
case RISCV::fixup_riscv_branch:
@@ -125,12 +115,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
125115
default:
126116
Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
127117
return ELF::R_RISCV_NONE;
128-
case RISCV::fixup_riscv_tlsdesc_load_lo12:
129-
return ELF::R_RISCV_TLSDESC_LOAD_LO12;
130-
case RISCV::fixup_riscv_tlsdesc_add_lo12:
131-
return ELF::R_RISCV_TLSDESC_ADD_LO12;
132-
case RISCV::fixup_riscv_tlsdesc_call:
133-
return ELF::R_RISCV_TLSDESC_CALL;
134118

135119
case FK_Data_1:
136120
Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
@@ -160,18 +144,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
160144
return ELF::R_RISCV_LO12_I;
161145
case RISCV::fixup_riscv_lo12_s:
162146
return ELF::R_RISCV_LO12_S;
163-
case RISCV::fixup_riscv_tprel_hi20:
164-
return ELF::R_RISCV_TPREL_HI20;
165-
case RISCV::fixup_riscv_tprel_lo12_i:
166-
return ELF::R_RISCV_TPREL_LO12_I;
167-
case RISCV::fixup_riscv_tprel_lo12_s:
168-
return ELF::R_RISCV_TPREL_LO12_S;
169-
case RISCV::fixup_riscv_tprel_add:
170-
return ELF::R_RISCV_TPREL_ADD;
171-
case RISCV::fixup_riscv_relax:
172-
return ELF::R_RISCV_RELAX;
173-
case RISCV::fixup_riscv_align:
174-
return ELF::R_RISCV_ALIGN;
175147
case RISCV::fixup_riscv_qc_e_32:
176148
return ELF::R_RISCV_QC_E_32;
177149
case RISCV::fixup_riscv_qc_abs20_u:

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h‎

Lines changed: 0 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -32,25 +32,6 @@ enum Fixups {
3232
// 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store
3333
// instructions
3434
fixup_riscv_pcrel_lo12_s,
35-
// 20-bit fixup corresponding to %got_pcrel_hi(foo) for instructions like
36-
// auipc
37-
fixup_riscv_got_hi20,
38-
// 20-bit fixup corresponding to %tprel_hi(foo) for instructions like lui
39-
fixup_riscv_tprel_hi20,
40-
// 12-bit fixup corresponding to %tprel_lo(foo) for instructions like addi
41-
fixup_riscv_tprel_lo12_i,
42-
// 12-bit fixup corresponding to %tprel_lo(foo) for the S-type store
43-
// instructions
44-
fixup_riscv_tprel_lo12_s,
45-
// Fixup corresponding to %tprel_add(foo) for PseudoAddTPRel, used as a linker
46-
// hint
47-
fixup_riscv_tprel_add,
48-
// 20-bit fixup corresponding to %tls_ie_pcrel_hi(foo) for instructions like
49-
// auipc
50-
fixup_riscv_tls_got_hi20,
51-
// 20-bit fixup corresponding to %tls_gd_pcrel_hi(foo) for instructions like
52-
// auipc
53-
fixup_riscv_tls_gd_hi20,
5435
// 20-bit fixup for symbol references in the jal instruction
5536
fixup_riscv_jal,
5637
// 12-bit fixup for symbol references in the branch instructions
@@ -65,18 +46,6 @@ enum Fixups {
6546
// Fixup representing a function call attached to the auipc instruction in a
6647
// pair composed of adjacent auipc+jalr instructions.
6748
fixup_riscv_call_plt,
68-
// Used to generate an R_RISCV_RELAX relocation, which indicates the linker
69-
// may relax the instruction pair.
70-
fixup_riscv_relax,
71-
// Used to generate an R_RISCV_ALIGN relocation, which indicates the linker
72-
// should fixup the alignment after linker relaxation.
73-
fixup_riscv_align,
74-
// Fixups indicating a TLS descriptor code sequence, corresponding to auipc,
75-
// lw/ld, addi, and jalr, respectively.
76-
fixup_riscv_tlsdesc_hi20,
77-
fixup_riscv_tlsdesc_load_lo12,
78-
fixup_riscv_tlsdesc_add_lo12,
79-
fixup_riscv_tlsdesc_call,
8049
// 12-bit fixup for symbol references in the 48-bit Xqcibi branch immediate
8150
// instructions
8251
fixup_riscv_qc_e_branch,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
181181
MCRegister Dest = MI.getOperand(1).getReg();
182182
int64_t Imm = MI.getOperand(2).getImm();
183183
Fixups.push_back(MCFixup::create(
184-
0, Expr, MCFixupKind(RISCV::fixup_riscv_tlsdesc_call), MI.getLoc()));
184+
0, Expr, FirstRelocationKind + ELF::R_RISCV_TLSDESC_CALL, MI.getLoc()));
185185
MCInst Call =
186186
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
187187

@@ -210,13 +210,13 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
210210

211211
// Emit the correct tprel_add relocation for the symbol.
212212
Fixups.push_back(MCFixup::create(
213-
0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
213+
0, Expr, FirstRelocationKind + ELF::R_RISCV_TPREL_ADD, MI.getLoc()));
214214

215-
// Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
215+
// Emit R_RISCV_RELAX for tprel_add where the relax feature is enabled.
216216
if (STI.hasFeature(RISCV::FeatureRelax)) {
217217
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
218218
Fixups.push_back(MCFixup::create(
219-
0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
219+
0, Dummy, FirstRelocationKind + ELF::R_RISCV_RELAX, MI.getLoc()));
220220
}
221221

222222
// Emit a normal ADD instruction with the given operands.
@@ -567,7 +567,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
567567
"getImmOpValue expects only expressions or immediates");
568568
const MCExpr *Expr = MO.getExpr();
569569
MCExpr::ExprKind Kind = Expr->getKind();
570-
RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
570+
unsigned FixupKind = RISCV::fixup_riscv_invalid;
571571
bool RelaxCandidate = false;
572572
if (Kind == MCExpr::Target) {
573573
const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
@@ -612,26 +612,26 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
612612
RelaxCandidate = true;
613613
break;
614614
case RISCVMCExpr::VK_GOT_HI:
615-
FixupKind = RISCV::fixup_riscv_got_hi20;
615+
FixupKind = FirstRelocationKind + ELF::R_RISCV_GOT_HI20;
616616
break;
617617
case RISCVMCExpr::VK_TPREL_LO:
618618
if (MIFrm == RISCVII::InstFormatI)
619-
FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
619+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_LO12_I;
620620
else if (MIFrm == RISCVII::InstFormatS)
621-
FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
621+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_LO12_S;
622622
else
623623
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
624624
RelaxCandidate = true;
625625
break;
626626
case RISCVMCExpr::VK_TPREL_HI:
627-
FixupKind = RISCV::fixup_riscv_tprel_hi20;
627+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_HI20;
628628
RelaxCandidate = true;
629629
break;
630630
case RISCVMCExpr::VK_TLS_GOT_HI:
631-
FixupKind = RISCV::fixup_riscv_tls_got_hi20;
631+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TLS_GOT_HI20;
632632
break;
633633
case RISCVMCExpr::VK_TLS_GD_HI:
634-
FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
634+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TLS_GD_HI20;
635635
break;
636636
case RISCVMCExpr::VK_CALL:
637637
FixupKind = RISCV::fixup_riscv_call;
@@ -642,16 +642,16 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
642642
RelaxCandidate = true;
643643
break;
644644
case RISCVMCExpr::VK_TLSDESC_HI:
645-
FixupKind = RISCV::fixup_riscv_tlsdesc_hi20;
645+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_HI20;
646646
break;
647647
case RISCVMCExpr::VK_TLSDESC_LOAD_LO:
648-
FixupKind = RISCV::fixup_riscv_tlsdesc_load_lo12;
648+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_LOAD_LO12;
649649
break;
650650
case RISCVMCExpr::VK_TLSDESC_ADD_LO:
651-
FixupKind = RISCV::fixup_riscv_tlsdesc_add_lo12;
651+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_ADD_LO12;
652652
break;
653653
case RISCVMCExpr::VK_TLSDESC_CALL:
654-
FixupKind = RISCV::fixup_riscv_tlsdesc_call;
654+
FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_CALL;
655655
break;
656656
case RISCVMCExpr::VK_QC_ABS20:
657657
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
@@ -689,9 +689,8 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
689689
// relaxed.
690690
if (EnableRelax && RelaxCandidate) {
691691
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
692-
Fixups.push_back(
693-
MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
694-
MI.getLoc()));
692+
Fixups.push_back(MCFixup::create(
693+
0, Dummy, FirstRelocationKind + ELF::R_RISCV_RELAX, MI.getLoc()));
695694
++MCNumFixups;
696695
}
697696

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