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[AArch64][GlobalISel] Fix EXTRACT_SUBREG reg classes in patterns to generate MULL. (llvm#136083)
This fixes the GISel warning "Skipped pattern: EXTRACT_SUBREG child #0 could not be coerced to a register class" by ensuring the register class is correct for the EXTRACT_SUBREG patterns. This most notably allows UMADDL / SMADDL patterns to be imported (many still do not work as a PatLeaf on a child cannot be generated at the moment).
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5 files changed

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‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2704,7 +2704,7 @@ multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
27042704

27052705
def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
27062706
(!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
2707-
(EXTRACT_SUBREG i64:$Rm, sub_32))>;
2707+
(EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
27082708

27092709
def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
27102710
(!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
@@ -5523,13 +5523,13 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
55235523
}
55245524

55255525
def : Pat<(f16 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
5526-
(!cast<Instruction>(NAME # HSr) (EXTRACT_SUBREG $Rn, ssub))>;
5526+
(!cast<Instruction>(NAME # HSr) (EXTRACT_SUBREG V128:$Rn, ssub))>;
55275527
def : Pat<(f64 (node (i32 (extractelt (v4i32 V128:$Rn), (i64 0))))),
5528-
(!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG $Rn, ssub))>;
5528+
(!cast<Instruction>(NAME # DSr) (EXTRACT_SUBREG V128:$Rn, ssub))>;
55295529
def : Pat<(f16 (node (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
5530-
(!cast<Instruction>(NAME # HDr) (EXTRACT_SUBREG $Rn, dsub))>;
5530+
(!cast<Instruction>(NAME # HDr) (EXTRACT_SUBREG V128:$Rn, dsub))>;
55315531
def : Pat<(f32 (node (i64 (extractelt (v2i64 V128:$Rn), (i64 0))))),
5532-
(!cast<Instruction>(NAME # SDr) (EXTRACT_SUBREG $Rn, dsub))>;
5532+
(!cast<Instruction>(NAME # SDr) (EXTRACT_SUBREG V128:$Rn, dsub))>;
55335533
}
55345534

55355535
//---

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -2557,15 +2557,15 @@ def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
25572557
def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
25582558

25592559
def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext_inreg GPR64:$Rm, i32))),
2560-
(SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
2560+
(SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;
25612561
def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext GPR32:$Rm))),
2562-
(SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
2562+
(SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;
25632563
def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
25642564
(SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
25652565
def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (and GPR64:$Rm, 0xFFFFFFFF))),
2566-
(UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
2566+
(UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;
25672567
def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (zext GPR32:$Rm))),
2568-
(UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
2568+
(UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;
25692569
def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
25702570
(UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
25712571

@@ -2609,44 +2609,44 @@ def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32),
26092609
(MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
26102610

26112611
def : Pat<(i64 (smullwithsignbits GPR64:$Rn, GPR64:$Rm)),
2612-
(SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
2612+
(SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;
26132613
def : Pat<(i64 (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm))),
2614-
(SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
2614+
(SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;
26152615

26162616
def : Pat<(i64 (add (smullwithsignbits GPR64:$Rn, GPR64:$Rm), GPR64:$Ra)),
2617-
(SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), GPR64:$Ra)>;
2617+
(SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;
26182618
def : Pat<(i64 (add (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)), GPR64:$Ra)),
2619-
(SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, GPR64:$Ra)>;
2619+
(SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;
26202620

26212621
def : Pat<(i64 (ineg (smullwithsignbits GPR64:$Rn, GPR64:$Rm))),
2622-
(SMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
2622+
(SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;
26232623
def : Pat<(i64 (ineg (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)))),
2624-
(SMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
2624+
(SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;
26252625

26262626
def : Pat<(i64 (sub GPR64:$Ra, (smullwithsignbits GPR64:$Rn, GPR64:$Rm))),
2627-
(SMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), GPR64:$Ra)>;
2627+
(SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;
26282628
def : Pat<(i64 (sub GPR64:$Ra, (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)))),
2629-
(SMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, GPR64:$Ra)>;
2629+
(SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;
26302630

26312631
def : Pat<(i64 (mul top32Zero:$Rn, top32Zero:$Rm)),
2632-
(UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
2632+
(UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;
26332633
def : Pat<(i64 (mul top32Zero:$Rn, (zext GPR32:$Rm))),
2634-
(UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
2634+
(UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;
26352635

26362636
def : Pat<(i64 (add (mul top32Zero:$Rn, top32Zero:$Rm), GPR64:$Ra)),
2637-
(UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), GPR64:$Ra)>;
2637+
(UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;
26382638
def : Pat<(i64 (add (mul top32Zero:$Rn, (zext GPR32:$Rm)), GPR64:$Ra)),
2639-
(UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, GPR64:$Ra)>;
2639+
(UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;
26402640

26412641
def : Pat<(i64 (ineg (mul top32Zero:$Rn, top32Zero:$Rm))),
2642-
(UMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
2642+
(UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;
26432643
def : Pat<(i64 (ineg (mul top32Zero:$Rn, (zext GPR32:$Rm)))),
2644-
(UMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
2644+
(UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;
26452645

26462646
def : Pat<(i64 (sub GPR64:$Ra, (mul top32Zero:$Rn, top32Zero:$Rm))),
2647-
(UMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), GPR64:$Ra)>;
2647+
(UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;
26482648
def : Pat<(i64 (sub GPR64:$Ra, (mul top32Zero:$Rn, (zext GPR32:$Rm)))),
2649-
(UMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, GPR64:$Ra)>;
2649+
(UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;
26502650
} // AddedComplexity = 5
26512651

26522652
def : MulAccumWAlias<"mul", MADDWrrr>;
@@ -7283,14 +7283,14 @@ multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, ValueType VTSVE
72837283
def : Pat<(VT128 (vector_insert VT128:$Rn,
72847284
(VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),
72857285
(i64 imm:$Immd))),
7286-
(INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn)>;
7286+
(INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG ZPR:$Rm, zsub)), SVEIdxTy:$Immn)>;
72877287

72887288
def : Pat<(VT64 (vector_insert VT64:$Rn,
72897289
(VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),
72907290
(i64 imm:$Immd))),
72917291
(EXTRACT_SUBREG
72927292
(INS (SUBREG_TO_REG (i64 0), VT64:$Rn, dsub), imm:$Immd,
7293-
(VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn),
7293+
(VT128 (EXTRACT_SUBREG ZPR:$Rm, zsub)), SVEIdxTy:$Immn),
72947294
dsub)>;
72957295
// Extracting from another NEON vector
72967296
def : Pat<(VT128 (vector_insert V128:$src,

‎llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -548,7 +548,7 @@ body: |
548548
; CHECK: liveins: $w0, $x1
549549
; CHECK-NEXT: {{ $}}
550550
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
551-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1
551+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
552552
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
553553
; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]]
554554
; CHECK-NEXT: $w0 = COPY [[LSLVWr]]

‎llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir‎

Lines changed: 72 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,12 @@ body: |
99
liveins: $w0
1010
1111
; CHECK-LABEL: name: shl_cimm_32
12-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
13-
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23
14-
; CHECK: $w0 = COPY [[UBFMWri]]
15-
; CHECK: RET_ReallyLR implicit $w0
12+
; CHECK: liveins: $w0
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
15+
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23
16+
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
17+
; CHECK-NEXT: RET_ReallyLR implicit $w0
1618
%0:gpr(s32) = COPY $w0
1719
%1:gpr(s32) = G_CONSTANT i32 8
1820
%2:gpr(s32) = G_SHL %0, %1(s32)
@@ -29,10 +31,12 @@ body: |
2931
liveins: $x0
3032
3133
; CHECK-LABEL: name: shl_cimm_64
32-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
33-
; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55
34-
; CHECK: $x0 = COPY [[UBFMXri]]
35-
; CHECK: RET_ReallyLR implicit $x0
34+
; CHECK: liveins: $x0
35+
; CHECK-NEXT: {{ $}}
36+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
37+
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55
38+
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
39+
; CHECK-NEXT: RET_ReallyLR implicit $x0
3640
%0:gpr(s64) = COPY $x0
3741
%1:gpr(s64) = G_CONSTANT i64 8
3842
%2:gpr(s64) = G_SHL %0, %1(s64)
@@ -49,10 +53,12 @@ body: |
4953
liveins: $w0
5054
5155
; CHECK-LABEL: name: lshr_cimm_32
52-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
53-
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31
54-
; CHECK: $w0 = COPY [[UBFMWri]]
55-
; CHECK: RET_ReallyLR implicit $w0
56+
; CHECK: liveins: $w0
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
59+
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31
60+
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
61+
; CHECK-NEXT: RET_ReallyLR implicit $w0
5662
%0:gpr(s32) = COPY $w0
5763
%3:gpr(s64) = G_CONSTANT i64 8
5864
%2:gpr(s32) = G_LSHR %0, %3(s64)
@@ -69,10 +75,12 @@ body: |
6975
liveins: $x0
7076
7177
; CHECK-LABEL: name: lshr_cimm_64
72-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
73-
; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63
74-
; CHECK: $x0 = COPY [[UBFMXri]]
75-
; CHECK: RET_ReallyLR implicit $x0
78+
; CHECK: liveins: $x0
79+
; CHECK-NEXT: {{ $}}
80+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
81+
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63
82+
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
83+
; CHECK-NEXT: RET_ReallyLR implicit $x0
7684
%0:gpr(s64) = COPY $x0
7785
%1:gpr(s64) = G_CONSTANT i64 8
7886
%2:gpr(s64) = G_LSHR %0, %1(s64)
@@ -89,10 +97,12 @@ body: |
8997
liveins: $w0
9098
9199
; CHECK-LABEL: name: ashr_cimm_32
92-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
93-
; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31
94-
; CHECK: $w0 = COPY [[SBFMWri]]
95-
; CHECK: RET_ReallyLR implicit $w0
100+
; CHECK: liveins: $w0
101+
; CHECK-NEXT: {{ $}}
102+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
103+
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31
104+
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
105+
; CHECK-NEXT: RET_ReallyLR implicit $w0
96106
%0:gpr(s32) = COPY $w0
97107
%3:gpr(s64) = G_CONSTANT i64 8
98108
%2:gpr(s32) = G_ASHR %0, %3(s64)
@@ -109,12 +119,14 @@ body: |
109119
liveins: $w0
110120
111121
; CHECK-LABEL: name: ashr_cimm_32_64
112-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
113-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
114-
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]]
115-
; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
116-
; CHECK: $w0 = COPY [[ASRVWr]]
117-
; CHECK: RET_ReallyLR implicit $w0
122+
; CHECK: liveins: $w0
123+
; CHECK-NEXT: {{ $}}
124+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
125+
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
126+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]].sub_32
127+
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
128+
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
129+
; CHECK-NEXT: RET_ReallyLR implicit $w0
118130
%0:gpr(s32) = COPY $w0
119131
%3:gpr(s64) = G_CONSTANT i64 -8
120132
%2:gpr(s32) = G_ASHR %0, %3(s64)
@@ -131,12 +143,14 @@ body: |
131143
liveins: $w0
132144
133145
; CHECK-LABEL: name: lshr_cimm_32_64
134-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
135-
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
136-
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]]
137-
; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
138-
; CHECK: $w0 = COPY [[LSRVWr]]
139-
; CHECK: RET_ReallyLR implicit $w0
146+
; CHECK: liveins: $w0
147+
; CHECK-NEXT: {{ $}}
148+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
149+
; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
150+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]].sub_32
151+
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
152+
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
153+
; CHECK-NEXT: RET_ReallyLR implicit $w0
140154
%0:gpr(s32) = COPY $w0
141155
%3:gpr(s64) = G_CONSTANT i64 -8
142156
%2:gpr(s32) = G_LSHR %0, %3(s64)
@@ -153,10 +167,12 @@ body: |
153167
liveins: $x0
154168
155169
; CHECK-LABEL: name: ashr_cimm_64
156-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
157-
; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63
158-
; CHECK: $x0 = COPY [[SBFMXri]]
159-
; CHECK: RET_ReallyLR implicit $x0
170+
; CHECK: liveins: $x0
171+
; CHECK-NEXT: {{ $}}
172+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
173+
; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63
174+
; CHECK-NEXT: $x0 = COPY [[SBFMXri]]
175+
; CHECK-NEXT: RET_ReallyLR implicit $x0
160176
%0:gpr(s64) = COPY $x0
161177
%1:gpr(s64) = G_CONSTANT i64 8
162178
%2:gpr(s64) = G_ASHR %0, %1(s64)
@@ -173,14 +189,16 @@ body: |
173189
liveins: $w0
174190
175191
; CHECK-LABEL: name: lshr_32_notimm64
176-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
177-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
178-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
179-
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
180-
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
181-
; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
182-
; CHECK: $w0 = COPY [[LSRVWr]]
183-
; CHECK: RET_ReallyLR implicit $w0
192+
; CHECK: liveins: $w0
193+
; CHECK-NEXT: {{ $}}
194+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
195+
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
196+
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
197+
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000
198+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
199+
; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
200+
; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
201+
; CHECK-NEXT: RET_ReallyLR implicit $w0
184202
%0:gpr(s32) = COPY $w0
185203
%3:gpr(s64) = G_CONSTANT i64 8
186204
%4:gpr(s64) = G_AND %3, %3
@@ -198,14 +216,16 @@ body: |
198216
liveins: $w0
199217
200218
; CHECK-LABEL: name: ashr_32_notimm64
201-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
202-
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
203-
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
204-
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
205-
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
206-
; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
207-
; CHECK: $w0 = COPY [[ASRVWr]]
208-
; CHECK: RET_ReallyLR implicit $w0
219+
; CHECK: liveins: $w0
220+
; CHECK-NEXT: {{ $}}
221+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
222+
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
223+
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
224+
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000
225+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
226+
; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
227+
; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
228+
; CHECK-NEXT: RET_ReallyLR implicit $w0
209229
%0:gpr(s32) = COPY $w0
210230
%3:gpr(s64) = G_CONSTANT i64 8
211231
%4:gpr(s64) = G_AND %3, %3

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