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[RISCV][VLOPT] Add support for Vector Fixed-Point Arithmetic Instructions (llvm#126483)
This patch adds the remaining support for fixed-point arithmetic instructions (we previously had support for averaging adds and subtracts). For saturating adds/subs/multiplies/clips, we can't change `vl` if `vxsat` is used, since changing `vl` may change its value. So this patch checks to see if it's dead before considering it a candidate.
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llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 37 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -979,6 +979,17 @@ static bool isSupportedInstr(const MachineInstr &MI) {
979979
case RISCV::VMV_V_I:
980980
case RISCV::VMV_V_X:
981981
case RISCV::VMV_V_V:
982+
// Vector Single-Width Saturating Add and Subtract
983+
case RISCV::VSADDU_VV:
984+
case RISCV::VSADDU_VX:
985+
case RISCV::VSADDU_VI:
986+
case RISCV::VSADD_VV:
987+
case RISCV::VSADD_VX:
988+
case RISCV::VSADD_VI:
989+
case RISCV::VSSUBU_VV:
990+
case RISCV::VSSUBU_VX:
991+
case RISCV::VSSUB_VV:
992+
case RISCV::VSSUB_VX:
982993
// Vector Single-Width Averaging Add and Subtract
983994
case RISCV::VAADDU_VV:
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case RISCV::VAADDU_VX:
@@ -988,6 +999,23 @@ static bool isSupportedInstr(const MachineInstr &MI) {
988999
case RISCV::VASUBU_VX:
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case RISCV::VASUB_VV:
9901001
case RISCV::VASUB_VX:
1002+
// Vector Single-Width Fractional Multiply with Rounding and Saturation
1003+
case RISCV::VSMUL_VV:
1004+
case RISCV::VSMUL_VX:
1005+
// Vector Single-Width Scaling Shift Instructions
1006+
case RISCV::VSSRL_VV:
1007+
case RISCV::VSSRL_VX:
1008+
case RISCV::VSSRL_VI:
1009+
case RISCV::VSSRA_VV:
1010+
case RISCV::VSSRA_VX:
1011+
case RISCV::VSSRA_VI:
1012+
// Vector Narrowing Fixed-Point Clip Instructions
1013+
case RISCV::VNCLIPU_WV:
1014+
case RISCV::VNCLIPU_WX:
1015+
case RISCV::VNCLIPU_WI:
1016+
case RISCV::VNCLIP_WV:
1017+
case RISCV::VNCLIP_WX:
1018+
case RISCV::VNCLIP_WI:
9911019

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// Vector Crypto
9931021
case RISCV::VWSLL_VI:
@@ -1187,8 +1215,16 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
11871215
const MCInstrDesc &Desc = MI.getDesc();
11881216
if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags))
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return false;
1190-
if (MI.getNumDefs() != 1)
1218+
1219+
if (MI.getNumExplicitDefs() != 1)
1220+
return false;
1221+
1222+
// Some instructions have implicit defs e.g. $vxsat. If they might be read
1223+
// later then we can't reduce VL.
1224+
if (!MI.allImplicitDefsAreDead()) {
1225+
LLVM_DEBUG(dbgs() << "Not a candidate because has non-dead implicit def\n");
11911226
return false;
1227+
}
11921228

11931229
if (MI.mayRaiseFPException()) {
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LLVM_DEBUG(dbgs() << "Not a candidate because may raise FP exception\n");

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -894,9 +894,10 @@ define void @test_dag_loop() {
894894
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmclr.m v0
897+
; CHECK-NEXT: vsetivli zero, 0, e8, m4, ta, ma
897898
; CHECK-NEXT: vmv.v.i v8, 0
898899
; CHECK-NEXT: vmv.v.i v12, 0
899-
; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu
900+
; CHECK-NEXT: vsetvli zero, zero, e8, m4, tu, mu
900901
; CHECK-NEXT: vssubu.vx v12, v8, zero, v0.t
901902
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
902903
; CHECK-NEXT: vmseq.vv v0, v12, v8

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