@@ -79,8 +79,9 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
7979 // "zero_reg" definition.
8080 if (DI->getDef ()->isSubClassOf (" Register" ) ||
8181 DI->getDef ()->getName () == " zero_reg" ) {
82- OperandMap[BaseIdx + i].Kind = OpData::Reg;
83- OperandMap[BaseIdx + i].Data .Reg = DI->getDef ();
82+ auto &Entry = OperandMap[BaseIdx + i];
83+ Entry.Kind = OpData::Reg;
84+ Entry.Data .Reg = DI->getDef ();
8485 ++OpsAdded;
8586 continue ;
8687 }
@@ -105,12 +106,14 @@ unsigned PseudoLoweringEmitter::addDagOperandMapping(
105106 OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
106107 OpsAdded += Insn.Operands [i].MINumOperands ;
107108 } else if (const IntInit *II = dyn_cast<IntInit>(Dag->getArg (i))) {
108- OperandMap[BaseIdx + i].Kind = OpData::Imm;
109- OperandMap[BaseIdx + i].Data .Imm = II->getValue ();
109+ auto &Entry = OperandMap[BaseIdx + i];
110+ Entry.Kind = OpData::Imm;
111+ Entry.Data .Imm = II->getValue ();
110112 ++OpsAdded;
111113 } else if (const auto *BI = dyn_cast<BitsInit>(Dag->getArg (i))) {
112- OperandMap[BaseIdx + i].Kind = OpData::Imm;
113- OperandMap[BaseIdx + i].Data .Imm = *BI->convertInitializerToInt ();
114+ auto &Entry = OperandMap[BaseIdx + i];
115+ Entry.Kind = OpData::Imm;
116+ Entry.Data .Imm = *BI->convertInitializerToInt ();
114117 ++OpsAdded;
115118 } else if (const DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg (i))) {
116119 // Just add the operands recursively. This is almost certainly
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