@@ -102,13 +102,13 @@ RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI)
102102 STI(STI) {}
103103
104104// The register used to hold the frame pointer.
105- static constexpr Register FPReg = RISCV::X8;
105+ static constexpr MCPhysReg FPReg = RISCV::X8;
106106
107107// The register used to hold the stack pointer.
108- static constexpr Register SPReg = RISCV::X2;
108+ static constexpr MCPhysReg SPReg = RISCV::X2;
109109
110110// The register used to hold the return address.
111- static constexpr Register RAReg = RISCV::X1;
111+ static constexpr MCPhysReg RAReg = RISCV::X1;
112112
113113// Offsets which need to be scale by XLen representing locations of CSRs which
114114// are given a fixed location by save/restore libcalls or Zcmp Push/Pop.
@@ -250,17 +250,17 @@ static int getLibCallID(const MachineFunction &MF,
250250 if (CSI.empty () || !RVFI->useSaveRestoreLibCalls (MF))
251251 return -1 ;
252252
253- Register MaxReg = RISCV::NoRegister ;
253+ Register MaxReg;
254254 for (auto &CS : CSI)
255255 // assignCalleeSavedSpillSlots assigns negative frame indexes to
256256 // registers which can be saved by libcall.
257257 if (CS.getFrameIdx () < 0 )
258258 MaxReg = std::max (MaxReg.id (), CS.getReg ().id ());
259259
260- if (MaxReg == RISCV::NoRegister )
260+ if (! MaxReg)
261261 return -1 ;
262262
263- switch (MaxReg) {
263+ switch (MaxReg. id () ) {
264264 default :
265265 llvm_unreachable (" Something has gone wrong!" );
266266 // clang-format off
@@ -339,7 +339,7 @@ getRestoreLibCallName(const MachineFunction &MF,
339339// representing registers to store/load.
340340static std::pair<unsigned , unsigned >
341341getPushPopEncodingAndNum (const Register MaxReg) {
342- switch (MaxReg) {
342+ switch (MaxReg. id () ) {
343343 default :
344344 llvm_unreachable (" Unexpected Reg for Push/Pop Inst" );
345345 case RISCV::X27: /* s11*/
@@ -1809,7 +1809,7 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
18091809 const TargetRegisterInfo *RegInfo = MF.getSubtarget ().getRegisterInfo ();
18101810
18111811 for (auto &CS : CSI) {
1812- unsigned Reg = CS.getReg ();
1812+ Register Reg = CS.getReg ();
18131813 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass (Reg);
18141814 unsigned Size = RegInfo->getSpillSize (*RC);
18151815
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