Skip to content

Commit f710478

Browse files
broxigarchenkosarev
authored and
Icohedron
committed
[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions (llvm#125561)
Generate op_sel operands for VOPC instructions --------- Co-authored-by: Ivan Kosarev <[email protected]>
1 parent ad87d54 commit f710478

File tree

9 files changed

+270
-258
lines changed

9 files changed

+270
-258
lines changed

‎llvm/lib/Target/AMDGPU/VOPCInstructions.td‎

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -389,10 +389,10 @@ multiclass VOPC_Pseudos <string opName,
389389
let SchedRW = P.Schedule;
390390
let isCompare = 1;
391391
let isCommutable = 1;
392-
let AsmMatchConverter =
393-
!if (P.HasOpSel, "cvtVOP3OpSel",
394-
!if (!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), "cvtVOP3",
395-
""));
392+
let AsmMatchConverter = !cond(
393+
P.HasOpSel : "cvtVOP3OpSel",
394+
!or(P.HasModifiers, P.HasOMod, P.HasIntClamp) : "cvtVOP3",
395+
1 : "");
396396
}
397397

398398
if P.HasExtSDWA then
@@ -454,6 +454,10 @@ multiclass VOPCX_Pseudos <string opName,
454454
let isCommutable = 1;
455455
let SubtargetPredicate = HasNoSdstCMPX;
456456
let IsVCMPX = 1;
457+
let AsmMatchConverter = !cond(
458+
P_NoSDst.HasOpSel : "cvtVOP3OpSel",
459+
!or(P_NoSDst.HasModifiers, P_NoSDst.HasOMod, P_NoSDst.HasIntClamp) : "cvtVOP3",
460+
1 : "");
457461
}
458462

459463
if P_NoSDst.HasExtSDWA then
@@ -1079,6 +1083,10 @@ multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
10791083
VCMPXNoSDstTable<1, opName#"_e64"> {
10801084
let Defs = !if(DefExec, [EXEC], []);
10811085
let SchedRW = p.Schedule;
1086+
let AsmMatchConverter = !cond(
1087+
p.HasOpSel : "cvtVOP3OpSel",
1088+
!or(p.HasModifiers, p.HasOMod, p.HasIntClamp) : "cvtVOP3",
1089+
1 : "");
10821090
}
10831091

10841092
if p.HasExtSDWA then
@@ -1127,6 +1135,10 @@ multiclass VOPCX_Class_Pseudos <string opName,
11271135
let Defs = [EXEC];
11281136
let SchedRW = P_NoSDst.Schedule;
11291137
let SubtargetPredicate = HasNoSdstCMPX;
1138+
let AsmMatchConverter = !cond(
1139+
P_NoSDst.HasOpSel : "cvtVOP3OpSel",
1140+
!or(P_NoSDst.HasModifiers, P_NoSDst.HasOMod, P_NoSDst.HasIntClamp) : "cvtVOP3",
1141+
1 : "");
11301142
}
11311143

11321144
if P_NoSDst.HasExtSDWA then

‎llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -128,19 +128,19 @@ v_cmp_class_f16_e64 vcc_lo, 0.5, m0
128128
// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
129129

130130
v_cmp_class_f16_e64 s5, v255.h, v2.l
131-
// W32: v_cmp_class_f16_e64 s5, v255.h, v2.l ; encoding: [0x05,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
131+
// W32: v_cmp_class_f16_e64 s5, v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
132132
// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
133133

134134
v_cmp_class_f16_e64 s5, s105, v255.h
135-
// W32: v_cmp_class_f16_e64 s5, s105, v255.h ; encoding: [0x05,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
135+
// W32: v_cmp_class_f16_e64 s5, s105, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
136136
// W64-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
137137

138138
v_cmp_class_f16_e64 s[10:11], v255.h, v2.l
139-
// W64: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
139+
// W64: v_cmp_class_f16_e64 s[10:11], v255.h, v2.l op_sel:[1,0,0] ; encoding: [0x0a,0x08,0x7d,0xd4,0xff,0x05,0x02,0x00]
140140
// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
141141

142142
v_cmp_class_f16_e64 s[10:11], s105, v255.h
143-
// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
143+
// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h op_sel:[0,1,0] ; encoding: [0x0a,0x10,0x7d,0xd4,0x69,0xfe,0x03,0x00]
144144
// W32-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
145145

146146
v_cmp_class_f32_e64 s5, v1, v2

‎llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopcx.s‎

Lines changed: 59 additions & 59 deletions
Large diffs are not rendered by default.

‎llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_promote.s‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 %s
33

44
v_cmp_class_f16 vcc, v1.h, v255.h
5-
// GFX11: v_cmp_class_f16_e64 vcc, v1.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x01,0xff,0x03,0x00]
5+
// GFX11: v_cmp_class_f16_e64 vcc, v1.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x01,0xff,0x03,0x00]
66

77
v_cmp_class_f16 vcc, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
88
// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
@@ -20,10 +20,10 @@ v_cmp_class_f16 vcc, v1.l, v255.l quad_perm:[3,2,1,0]
2020
// GFX11: v_cmp_class_f16_e64_dpp vcc, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
2121

2222
v_cmp_class_f16 vcc, v127.h, v255.h
23-
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]
23+
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]
2424

2525
v_cmp_class_f16 vcc, v127.h, v255.h
26-
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]
26+
// GFX11: v_cmp_class_f16_e64 vcc, v127.h, v255.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x7f,0xff,0x03,0x00]
2727

2828
v_cmp_class_f16 vcc, v127.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
2929
// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.h, v255.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0xfe,0x03,0x00,0x7f,0x77,0x39,0x05]
@@ -56,10 +56,10 @@ v_cmp_class_f16 vcc, v127.l, v255.l quad_perm:[3,2,1,0]
5656
// GFX11: v_cmp_class_f16_e64_dpp vcc, v127.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0xfe,0x03,0x00,0x7f,0x1b,0x00,0xff]
5757

5858
v_cmp_class_f16 vcc, v128.h, v2.h
59-
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]
59+
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]
6060

6161
v_cmp_class_f16 vcc, v128.h, v2.h
62-
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]
62+
// GFX11: v_cmp_class_f16_e64 vcc, v128.h, v2.h op_sel:[1,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0x80,0x05,0x02,0x00]
6363

6464
v_cmp_class_f16 vcc, v128.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
6565
// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.h, v2.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x6a,0x18,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x80,0x77,0x39,0x05]
@@ -92,10 +92,10 @@ v_cmp_class_f16 vcc, v128.l, v2.l quad_perm:[3,2,1,0]
9292
// GFX11: v_cmp_class_f16_e64_dpp vcc, v128.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x80,0x1b,0x00,0xff]
9393

9494
v_cmp_class_f16 vcc, vcc_hi, v255.h
95-
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
95+
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
9696

9797
v_cmp_class_f16 vcc, vcc_hi, v255.h
98-
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
98+
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
9999

100100
v_cmp_class_f16 vcc, vcc_hi, v255.l
101101
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
@@ -104,10 +104,10 @@ v_cmp_class_f16 vcc, vcc_hi, v255.l
104104
// GFX11: v_cmp_class_f16_e64 vcc, vcc_hi, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6b,0xfe,0x03,0x00]
105105

106106
v_cmp_class_f16 vcc, vcc_lo, v255.h
107-
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
107+
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
108108

109109
v_cmp_class_f16 vcc, vcc_lo, v255.h
110-
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
110+
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.h op_sel:[0,1,0] ; encoding: [0x6a,0x10,0x7d,0xd4,0x6a,0xfe,0x03,0x00]
111111

112112
v_cmp_class_f16 vcc, vcc_lo, v255.l
113113
// GFX11: v_cmp_class_f16_e64 vcc, vcc_lo, v255.l ; encoding: [0x6a,0x00,0x7d,0xd4,0x6a,0xfe,0x03,0x00]

0 commit comments

Comments
 (0)