Recommit "[RISCV] Prefer (select (x < 0), y, z) -> x >> (XLEN - 1) & (y - z) + z even with Zicond. (llvm#125772)"

With the test changes.

Original message:

The Zicond version of this requires an li instruction and an
additional register.

Without Zicond we match this in a DAGCombine on RISCVISD::SELECT_CC.

This PR has 2 commits. I'll pre-commit the test change if this looks
good.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -8460,6 +8460,33 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
     if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV)) {
       const APInt &TrueVal = TrueV->getAsAPIntVal();
       const APInt &FalseVal = FalseV->getAsAPIntVal();
+
+      // Prefer these over Zicond to avoid materializing an immediate:
+      //   (select (x < 0), y, z)  -> x >> (XLEN - 1) & (y - z) + z
+      //   (select (x > -1), z, y) -> x >> (XLEN - 1) & (y - z) + z
+      if (CondV.getOpcode() == ISD::SETCC &&
+          CondV.getOperand(0).getValueType() == VT && CondV.hasOneUse()) {
+        ISD::CondCode CCVal = cast<CondCodeSDNode>(CondV.getOperand(2))->get();
+        if ((CCVal == ISD::SETLT && isNullConstant(CondV.getOperand(1))) ||
+            (CCVal == ISD::SETGT && isAllOnesConstant(CondV.getOperand(1)))) {
+          int64_t TrueImm = TrueVal.getSExtValue();
+          int64_t FalseImm = FalseVal.getSExtValue();
+          if (CCVal == ISD::SETGT)
+            std::swap(TrueImm, FalseImm);
+          if (isInt<12>(TrueImm) && isInt<12>(FalseImm) &&
+              isInt<12>(TrueImm - FalseImm)) {
+            SDValue SRA =
+                DAG.getNode(ISD::SRA, DL, VT, CondV.getOperand(0),
+                            DAG.getConstant(Subtarget.getXLen() - 1, DL, VT));
+            SDValue AND =
+                DAG.getNode(ISD::AND, DL, VT, SRA,
+                            DAG.getSignedConstant(TrueImm - FalseImm, DL, VT));
+            return DAG.getNode(ISD::ADD, DL, VT, AND,
+                               DAG.getSignedConstant(FalseImm, DL, VT));
+          }
+        }
+      }
+
       const int TrueValCost = RISCVMatInt::getIntMatCost(
           TrueVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
       const int FalseValCost = RISCVMatInt::getIntMatCost(

llvm/test/CodeGen/RISCV/select-const.ll

@@ -445,98 +445,38 @@ define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
 }
 
 define i32 @select_slt_zero_constant1_constant2(i32 signext %x) {
-; RV32I-LABEL: select_slt_zero_constant1_constant2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srai a0, a0, 31
-; RV32I-NEXT:    andi a0, a0, 10
-; RV32I-NEXT:    addi a0, a0, -3
-; RV32I-NEXT:    ret
-;
-; RV32IF-LABEL: select_slt_zero_constant1_constant2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    srai a0, a0, 31
-; RV32IF-NEXT:    andi a0, a0, 10
-; RV32IF-NEXT:    addi a0, a0, -3
-; RV32IF-NEXT:    ret
-;
-; RV32ZICOND-LABEL: select_slt_zero_constant1_constant2:
-; RV32ZICOND:       # %bb.0:
-; RV32ZICOND-NEXT:    slti a0, a0, 0
-; RV32ZICOND-NEXT:    li a1, -10
-; RV32ZICOND-NEXT:    czero.nez a0, a1, a0
-; RV32ZICOND-NEXT:    addi a0, a0, 7
-; RV32ZICOND-NEXT:    ret
-;
-; RV64I-LABEL: select_slt_zero_constant1_constant2:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srai a0, a0, 63
-; RV64I-NEXT:    andi a0, a0, 10
-; RV64I-NEXT:    addi a0, a0, -3
-; RV64I-NEXT:    ret
-;
-; RV64IFD-LABEL: select_slt_zero_constant1_constant2:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    srai a0, a0, 63
-; RV64IFD-NEXT:    andi a0, a0, 10
-; RV64IFD-NEXT:    addi a0, a0, -3
-; RV64IFD-NEXT:    ret
+; RV32-LABEL: select_slt_zero_constant1_constant2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    andi a0, a0, 10
+; RV32-NEXT:    addi a0, a0, -3
+; RV32-NEXT:    ret
 ;
-; RV64ZICOND-LABEL: select_slt_zero_constant1_constant2:
-; RV64ZICOND:       # %bb.0:
-; RV64ZICOND-NEXT:    slti a0, a0, 0
-; RV64ZICOND-NEXT:    li a1, -10
-; RV64ZICOND-NEXT:    czero.nez a0, a1, a0
-; RV64ZICOND-NEXT:    addi a0, a0, 7
-; RV64ZICOND-NEXT:    ret
+; RV64-LABEL: select_slt_zero_constant1_constant2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    andi a0, a0, 10
+; RV64-NEXT:    addi a0, a0, -3
+; RV64-NEXT:    ret
   %cmp = icmp slt i32 %x, 0
   %cond = select i1 %cmp, i32 7, i32 -3
   ret i32 %cond
 }
 
 define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) {
-; RV32I-LABEL: select_sgt_negative_one_constant1_constant2:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    srai a0, a0, 31
-; RV32I-NEXT:    andi a0, a0, -10
-; RV32I-NEXT:    addi a0, a0, 7
-; RV32I-NEXT:    ret
-;
-; RV32IF-LABEL: select_sgt_negative_one_constant1_constant2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    srai a0, a0, 31
-; RV32IF-NEXT:    andi a0, a0, -10
-; RV32IF-NEXT:    addi a0, a0, 7
-; RV32IF-NEXT:    ret
-;
-; RV32ZICOND-LABEL: select_sgt_negative_one_constant1_constant2:
-; RV32ZICOND:       # %bb.0:
-; RV32ZICOND-NEXT:    slti a0, a0, 0
-; RV32ZICOND-NEXT:    li a1, -10
-; RV32ZICOND-NEXT:    czero.eqz a0, a1, a0
-; RV32ZICOND-NEXT:    addi a0, a0, 7
-; RV32ZICOND-NEXT:    ret
-;
-; RV64I-LABEL: select_sgt_negative_one_constant1_constant2:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    srai a0, a0, 63
-; RV64I-NEXT:    andi a0, a0, -10
-; RV64I-NEXT:    addi a0, a0, 7
-; RV64I-NEXT:    ret
-;
-; RV64IFD-LABEL: select_sgt_negative_one_constant1_constant2:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    srai a0, a0, 63
-; RV64IFD-NEXT:    andi a0, a0, -10
-; RV64IFD-NEXT:    addi a0, a0, 7
-; RV64IFD-NEXT:    ret
+; RV32-LABEL: select_sgt_negative_one_constant1_constant2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    andi a0, a0, -10
+; RV32-NEXT:    addi a0, a0, 7
+; RV32-NEXT:    ret
 ;
-; RV64ZICOND-LABEL: select_sgt_negative_one_constant1_constant2:
-; RV64ZICOND:       # %bb.0:
-; RV64ZICOND-NEXT:    slti a0, a0, 0
-; RV64ZICOND-NEXT:    li a1, -10
-; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
-; RV64ZICOND-NEXT:    addi a0, a0, 7
-; RV64ZICOND-NEXT:    ret
+; RV64-LABEL: select_sgt_negative_one_constant1_constant2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    andi a0, a0, -10
+; RV64-NEXT:    addi a0, a0, 7
+; RV64-NEXT:    ret
   %cmp = icmp sgt i32 %x, -1
   %cond = select i1 %cmp, i32 7, i32 -3
   ret i32 %cond