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docs/psoc-edge: Added Pins and GPIO docs.
Signed-off-by: jaenrig-ifx <[email protected]>
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‎docs/psoc-edge/general.rst‎

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.. _psoc_edge_general:
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.. include:: links.rst
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General information about the PSOC™ Edge port
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==============================================
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************************
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Links for product details:
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* `KIT_PSE84_AI product page with relevant documents <https://www.infineon.com/evaluation-board/KIT-PSE84-AI>`_
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* `KIT_PSE84_AI MCU Datasheet <TODO: TO BE ADDED>`_
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* `KIT_PSE84_AI PSOC™ Edge E84 AI product page <pse84_kit_ai_product_page_>`_
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* `KIT_PSE84_AI PSOC™ Edge E84 AI Kit guide <pse84_kit_ai_guide_>`_
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* `PSOC™ Edge E8x2, E8x3, E8x5, E8x6 Consumer Datasheet <pse8x_consumer_datasheet_>`_
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* `PSOC™ Edge E8x2, E8x3, E8x5, E8x6 Architecture Reference Manual <pse8x_arch_ref_manual_>`_

‎docs/psoc-edge/links.rst‎

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.. _links.rst:
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.. _pse84_kit_ai_product_page: https://www.infineon.com/evaluation-board/KIT-PSE84-AI
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.. _pse84_kit_ai_guide: https://www.infineon.com/assets/row/public/documents/30/44/infineon-kit-pse84-ai-user-guide-usermanual-en.pdf
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.. _pse8x_consumer_datasheet: https://www.infineon.com/assets/row/public/documents/30/49/infineon-psoc-edge-e8x-consumer-datasheet-datasheet-en.pdf
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.. _pse8x_arch_ref_manual: https://www.infineon.com/assets/row/public/documents/30/57/infineon-psoc-edge-e8x-architecture-reference-manual-additionaltechnicalinformation-en.pdf

‎docs/psoc-edge/quickref.rst‎

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.. _psoc_edge_quickref:
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.. include:: links.rst
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Quick reference for the PSOC™ Edge
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===================================
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general.rst
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installation.rst
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installation.rst
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Pins and GPIO
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-------------
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See :ref:`machine.Pin <machine.Pin>` for the complete Pin API reference.
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This section focuses on the specific PSOC™ Edge port variations and particularities.
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The constructor
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^^^^^^^^^^^^^^^
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The controller pin naming follows the nomenclature ``P<port>_<pin>``, where:
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- ``<port>`` is a numeric identifier for the port (e.g., 0-21 for the PSOC™ Edge E84)
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- ``<pin>`` is the pin number within that port.
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Use the respective board pinout diagram to find the available pins and their locations.
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This is the ``id`` that needs to be passed to the constructor in one of the following formats:
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- As a **string label**, single or double quoted: ``'P<port>_<pin>'`` or ``"P<port>_<pin>"``
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- A **pre-instantiated object** ``Pin.cpu.<pin>`` or ``Pin.board.<pin>``.
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::
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from machine import Pin
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p_in = Pin('P0_0', Pin.IN)
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p_out = Pin("P7_0", Pin.OUT, value=False)
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p = Pin(Pin.cpu.P17_1, Pin.OPEN_DRAIN)
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The pre-instantiated object can be used directly without calling the constructor.
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Instead, you can use ``init()`` to configure it.
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::
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from machine import Pin
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pin = Pin.cpu.P17_0
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pin.init(mode=Pin.IN)
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.. tip::
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Use the REPL interface to discover the available user pins, using tab for completion:
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>>> from machine import Pin
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>>> Pin.cpu.P
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P10_5 P10_7 P11_3 P12_3
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P13_0 P13_1 P13_2 P13_3
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P13_4 P13_5 P13_6 P13_7
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P14_0 P14_1 P14_2 P14_3
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P14_4 P14_5 P14_6 P14_7
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P15_0 P15_1 P15_2 P15_3
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P15_4 P15_5 P15_6 P15_7
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P16_0 P16_1 P16_2 P16_3
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P16_4 P16_5 P16_6 P16_7
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P17_0 P17_1 P17_2 P17_3
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P17_4 P17_5 P17_7 P20_3
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P20_4 P20_5 P20_6 P20_7
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P21_1 P21_2 P21_3 P21_4
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P21_5 P21_6 P21_7 P3_0
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P3_1 P6_4 P6_6 P7_0
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P7_7 P8_0 P8_1 P8_5
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P8_6 P9_0 P9_1 P9_2
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P9_3
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.. Add Pin.board.xxx when we define some pins. This will be more helpful.
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.. warning::
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Currently no ``Pin.board.<pin>`` are defined for the PSOC™ Edge E84 AI Kit.
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In addition to the supported ``pull`` configuration values, ``PULL_UP_DOWN`` is also available in this port.
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The ``drive`` parameter accepts up to 8 levels, which set the following drive strength for the pin:
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- ``DRIVE_0``: 1mA/2mA drive current (normal/high speed IO)
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- ``DRIVE_1``: 2mA/4mA drive current (normal/high speed IO)
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- ``DRIVE_2``: 3mA/6mA drive current (normal/high speed IO)
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- ``DRIVE_3``: 4mA/8mA drive current (normal/high speed IO)
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- ``DRIVE_4``: 5mA/10mA drive current (normal/high speed IO)
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- ``DRIVE_5``: 6mA/12mA drive current (normal/high speed IO)
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- ``DRIVE_6``: 7mA/14mA drive current (normal/high speed IO)
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- ``DRIVE_7``: 8mA/16mA drive current (normal/high speed IO)
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For more information about drive strength, check the PSOC™ Edge `Datasheet <pse8x_consumer_datasheet_>`_ and `Architecture Reference Manual <pse8x_arch_ref_manual_>`_.
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.. note::
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The following constructor arguments and/or configuration values are NOT supported in this port:
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- ``alt``: Alternate functionality is not supported.
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- ``mode``: ``Pin.ALT``, ``Pin.ALT_OPEN_DRAIN``, and ``Pin.ANALOG`` modes are not supported.
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Methods
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^^^^^^^
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.. method:: Pin.irq(handler=None, trigger=(Pin.IRQ_FALLING | Pin.IRQ_RISING), priority=7, wake=None, hard=False)
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This port has a few variations from the standard machine API for the ``irq()`` function:
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- ``handler``: The handler function currently does not accept any arguments.
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- ``priority``: Priority values range from 7 (lowest) to 0 (highest).
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.. note::
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All pins on the same port share the same interrupt line. Therefore, only one priority can be set for all pins on the same port.
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If multiple pins configure interrupts for the same port, the highest priority will be used.
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If only one pin is configured for an interrupt, its priority can be reconfigured to any value.
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.. note::
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The following ``irq()`` features are not supported in this port:
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- ``trigger``: The ``Pin.IRQ_LOW_LEVEL`` and ``Pin.IRQ_HIGH_LEVEL`` triggers are not supported.
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- ``wake``: The wake parameter is currently not supported.
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- ``hard``: This parameter is ignored. It can be passed but currently has no effect.
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.. note::
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**None** of the non-core methods from the Pin API are currently implemented for this port.

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