improve en

rafaelcorsi · rafaelcorsi · commit 763e0f04055d · 2025-08-06T09:16:01.000-03:00
diff --git a/docs-src/Entrega-1.md b/docs-src/Entrega-1.md
@@ -1,4 +1,4 @@
-# 🔔 Assigment 1
+# 🔔 Assessment 1
 
 !!! tip "Deliver"
     What should be delivered?
diff --git a/docs-src/Entrega-2.md b/docs-src/Entrega-2.md
@@ -1,4 +1,4 @@
-# 🔔 Assigment 2 
+# 🔔 Assessment 2 
 
 !!! tip "Deliver"
     What should be delivered?
@@ -14,9 +14,9 @@ For this, it will be necessary to modify the project created in the tutorial to
 - PIO peripheral that handles the button must generate an interrupt
 - Program memory separated from data memory
 
-Once the JTAG starts generating interrupts, it will no longer be necessary to use the JTAG *small driver*, remember to change this in the **bsp**.
+Once the JTAG starts generating interrupts, it will no longer be necessary to use the JTAG *small driver*. Remember to change this in the **bsp**.
 
-Start by reading the buttons without interruption, once it is working, use the following sites as a reference to implement interruption in NIOS:
+Start by reading the buttons without interruption. Once it is working, use the following sites as a reference to implement interruption in NIOS:
 
 Tips:
 
@@ -36,7 +36,7 @@ Tips:
     - Interrupt in button reading
 - C
     - Data memory separated from program memory
-    - JTAG generating interrupt.
+    - JTAG generating interrupt
     - PIO dedicated to reading buttons (SWx) and controlling `EN` and `DIR`
 - D 
     - Delivered only the tutorial
diff --git a/docs-src/Entrega-3.md b/docs-src/Entrega-3.md
@@ -1,9 +1,9 @@
-# 🔔 Assigment 3
+# 🔔 Assessment 3
 
- What should be delivered?
+What should be delivered?
 
 - **Folder:** `Entrega_3_FPGA_NIOS_IP`
-- **Video** of the project working with an explanation (approx 1.5 min)   
+- **Video** of the project working with an explanation (approx. 1.5 min)   
 
 In this delivery, we will encapsulate the peripheral we created to control the stepper motor (`Entrega-1`) in Platform Designer (creating a memory-mapped peripheral) so that we have a dedicated component to control the motor.
 
@@ -24,7 +24,6 @@ The control logic must interface with the Stepper Motor peripheral on all contro
 | 2      | VEL          | R/W  |
 | ...    | ...          |      |
 
-
 The table above maps each address of the peripheral to a different functionality. In this example, if the user wants to activate the motor, they must write to address 0 of this peripheral.
 
 > Note that some addresses are Read Only and others are Read/Write (type). This is because it doesn't make sense (nor is it physically possible) to write to some addresses.
@@ -37,7 +36,7 @@ The table above maps each address of the peripheral to a different functionality
 In addition to the HW part, we will develop a C library that will abstract the interface with this peripheral. 
 The peripheral must have a driver capable of interacting with it. We will standardize some functions to define a standard interface:
 
-``` c
+```c
 // For rubric C
 int motor_init( ..... );        // Initializes the peripheral
 int motor_halt( ..... );        // Deactivates the peripheral 
@@ -48,9 +47,10 @@ int motor_en( ..... );          // Returns if there was any click
 
 Add the following functions (each one + half a concept):
 
-``` c
+```c
 // For rubric B/A
 int motor_dir( ..... );      // sets direction
 int motor_vel( ..... );      // sets speed
 ```
 This driver should be distributed in two files: `motor.c` and `motor.h`.
+This driver should be distributed in two files: `motor.c` and `motor.h`.
diff --git a/docs-src/Entrega-4.md b/docs-src/Entrega-4.md
@@ -1,4 +1,4 @@
-# 🔔 Assigment 4
+# 🔔 Assessment 4
 
 !!! tip "Deliver"
     What should be delivered?
diff --git a/docs-src/Entrega-5.md b/docs-src/Entrega-5.md
@@ -1,4 +1,4 @@
-# 🔔 Assignment 5
+# 🔔 Assessment 5
 
 !!! tip "Deliver"
     What should be delivered?
diff --git a/docs-src/Entrega-6.md b/docs-src/Entrega-6.md
@@ -1,4 +1,4 @@
-# 🔔 HPS+FPGA - Assigment 1
+# 🔔 Assessment 6
 
 Você pode escolher entre um dos temas a seguir:
 
diff --git a/docs-src/Entrega-Extra-1.md b/docs-src/Entrega-Extra-1.md
@@ -3,7 +3,7 @@
 Now that we've seen how to interface ARM with FPGA, how about adding the peripheral you created in assignment 2 (the `peripheral_led`) and controlling the FPGA LEDs via Linux with your own peripheral?
 
 1. Modify Platform Designer by adding your IP
-   - Note the address
+   - Note the address 
 1. Compile the project, generate the `.rbf` and `.dtb` (copy to the SD card)
 1. Modify `main.c` to access your peripheral
 1. Test
diff --git a/docs-src/Tutorial-Acelerando-HLS.md b/docs-src/Tutorial-Acelerando-HLS.md
@@ -8,11 +8,11 @@ HLS (High-Level Synthesis Compiler) is a compilation tool that allows us to crea
 
 <iframe width="560" height="315" src="https://www.youtube.com/embed/hEbfAU_1x8k" frameborder="0" allow="accelerometer; autoplay; encrypted-media; gyroscope; picture-in-picture" allowfullscreen></iframe>
 
-## centos
+## CentOS
 
 !!! warning
-    I was only able to get it working on centos6; my solution was to run
-    a docker with centos and install the dependencies there. I run HLS via the
+    I was only able to get it working on CentOS 6; my solution was to run
+    a docker with CentOS and install the dependencies there. I run HLS via the
     docker CLI. 
     
 !!! note
diff --git a/docs-src/Tutorial-FPGA-NIOS-IP.md b/docs-src/Tutorial-FPGA-NIOS-IP.md
@@ -1,4 +1,4 @@
-#  IP Core
+# IP Core
 
 In this tutorial, we will develop a custom peripheral for the NIOS processor, dedicated to controlling the board's LEDs. The peripheral will have an internal register bank for its control, and a "memory-mapped I/O" interface so we can control it from NIOS (using C code).
 
@@ -10,7 +10,7 @@ To follow this tutorial, you need:
 - **Software:** Quartus 18.01 
     - Modelsim Simulator
 
-Git submission:
+Submission on git:
 
 - **Folder:** `Lab3_FPGA_IP/`
 
@@ -345,7 +345,7 @@ Now add the component to the project and make the correct connections (as if it
 
 ![](figs/Tutorial-FPGA-IP_final.png)
 
-Generate the component: Click on `Generate HDL` :arrow_right: `Generate`. 
+Generate the component: Click on `Generate` :arrow_right: `Generate`. 
 
 !!! warning ""
     Check the option: ✅ `Create a Simulation Model`
diff --git a/docs-src/info-FPGA-e-Softwares.md b/docs-src/info-FPGA-e-Softwares.md
@@ -4,7 +4,6 @@ Throughout the course, we will mainly work with Intel SoC FPGAs. The main develo
 
 The development software for Intel FPGAs is called Quartus, and it has many versions and variations. Download the one indicated here to avoid having to reinstall everything.
 
-
 !!! note "2020-2 Online Version"
     You will receive the following materials to work on the course from home:
     
@@ -50,3 +49,4 @@ Along with Quartus installation, some other software is installed:
 :heavy_check_mark: Linux
 :no_entry_sign: Windows
 :no_entry_sign: MAC
+:no_entry_sign: MAC
diff --git a/docs-src/info-HPS-Serial.md b/docs-src/info-HPS-Serial.md
@@ -15,7 +15,7 @@ Linux on the HPS is usually configured (in the bootloader) to have a terminal re
 
 Once the USB port is connected to the PC and the board is powered on, we can check which *device* the serial port was mapped to (on the `host`):
 
-``` bash
+```bash
 $ dmesg | tail 
 [95158.497894] ftdi_sio 1-1.1:1.0: device disconnected
 [95161.649187] usb 1-1.1: new full-speed USB device number 22 using xhci_hcd
@@ -26,7 +26,7 @@ $ dmesg | tail
 
 In the log, we see that an **FTDI USB Serial Device** was connected to **ttyUSB0**. We can then open the terminal with any serial port program (PUTTY, ...), in this example we will use the **screen** program.
 
-``` bash
+```bash
 $ screen /dev/ttyUSB0 115200,cs8
 ```
 
diff --git a/docs-src/info-SDcard.md b/docs-src/info-SDcard.md
@@ -1,6 +1,6 @@
 # Updating the SDCARD
 
-Information on how to update the sdcard.
+Information on how to update the SD card.
 
 ## Updating the preload
 
@@ -22,13 +22,13 @@ To update the kernel, simply mount partition 0 (819.2 MB). In my case, the path
 
 The `zImage` file is located (inside the kernel repository) at: `/arch/arm/boot/zImage`
 
-```
+```bash
 $ cp ~/work/linux/arch/arm/boot/zImage /run/media/corsi/B0DA-B234/
 $ sync
 ```
 
 !!! note
-    You will need to edit for the path where the partition was mounted on your Linux.
+    You will need to edit the path where the partition was mounted on your Linux.
 
 When you do this, you will notice that the Linux kernel version is the one generated in the kernel compilation step.
 
@@ -38,10 +38,10 @@ TBD
 
 ## FileSystem
 
-To insert our fileSystem into the SDCARD, first mount partition 1. In my case: `/media/corsi/9cb79fd9-69b8-43e3-bcfe-fa4582579e2c/`. Once mounted, you should first delete the files saved there (remove the old fileSystem) and then extract what was generated by buildroot.
+To insert our file system into the SD card, first mount partition 1. In my case: `/media/corsi/9cb79fd9-69b8-43e3-bcfe-fa4582579e2c/`. Once mounted, you should first delete the files saved there (remove the old file system) and then extract what was generated by buildroot.
 
 !!! warning
-    You will need to edit for the path where the partition was mounted on your Linux. The partition is the one that contains the root `/` of the embedded Linux.
+    You will need to edit the path where the partition was mounted on your Linux. The partition is the one that contains the root `/` of the embedded Linux.
 
 !!! danger
     If you make a mistake, it can be destructive (for your files)
diff --git a/mkdocs.yml b/mkdocs.yml
@@ -80,24 +80,24 @@ nav:
   - Home: index.md
   - FPGA:
       - 1.  FPGA RTL: "Tutorial-FPGA-RTL.md"
-      - 🔔 Assigment: "Entrega-1.md"
+      - 🔔 Assessment: "Entrega-1.md"
       - 2.  FPGA NIOS: "Tutorial-FPGA-NIOS.md"
-      - 🔔 Assigment: "Entrega-2.md"
+      - 🔔 Assessment: "Entrega-2.md"
       - 3.  FPGA NIOS IP: "Tutorial-FPGA-NIOS-IP.md"
-      - 🔔 Assigment: "Entrega-3.md"
+      - 🔔 Assessment: "Entrega-3.md"
  
   - HPS:
       - 4. HPS: "Tutorial-HPS.md"
       - 5. HPS-Running: "Tutorial-HPS-Running.md"
       - 6. HPS-BuildSystem: "Tutorial-HPS-BuildSystem.md"
       - 7. HPS-BlinkLED: "Tutorial-HPS-BlinkLED.md"
       -  Extra - Network: "info-HPS-ethernet.md"
-      - 🔔 Assigment: "Entrega-4.md"
+      - 🔔 Assessment: "Entrega-4.md"
 
       - 8. HPS-Kernel: "Tutorial-HPS-Kernel.md"
       - 9. HPS-Buildroot: "Tutorial-HPS-Buildroot.md"
       - 10. Extra - HPS-buildroot-scripts: "info-HPS-buildroot-scripts.md"
-      - 🔔 Assigment: "Entrega-5.md"
+      - 🔔 Assessment: "Entrega-5.md"
       
       - 11. HPS-DeviceDriver: "Tutorial-HPS-DeviceDriver.md"
       - 12. HPS-Kernel-Module: "Tutorial-HPS-kernel-module.md"
@@ -106,12 +106,12 @@ nav:
   - HPS + FPGA:
       - 14. HPS-FPGA-BlinkLED: "Tutorial-HPS-FPGA-BlinkLED.md"
       - 15. HPS-FPGA-VGA: "Tutorial-HPS-FPGA-VGA.md"
-      - 🔔 Assigment:  "Entrega-6.md"
+      - 🔔 Assessment:  "Entrega-6.md"
       - 16. HPS-FPGA-Kernel-Char_LED_Driver: "Tutorial-HPS-FPGA-kernel-char-led-driver.md"
       
   - High Level Synthesis:
       - 17.  Acelerando-HLS: "Tutorial-Acelerando-HLS.md"
-      - 🔔 Assigment:"Entrega-Extra-1.md"
+      - 🔔 Assessment:"Entrega-Extra-1.md"
 
   - "Useful":
       - Softwares: "info-FPGA-e-Softwares.md"

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-# 🔔 Assigment 1`
	`1`	`+# 🔔 Assessment 1`
`2`	`2`
`3`	`3`	`!!! tip "Deliver"`
`4`	`4`	`What should be delivered?`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-# 🔔 Assigment 4`
	`1`	`+# 🔔 Assessment 4`
`2`	`2`
`3`	`3`	`!!! tip "Deliver"`
`4`	`4`	`What should be delivered?`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-# 🔔 Assignment 5`
	`1`	`+# 🔔 Assessment 5`
`2`	`2`
`3`	`3`	`!!! tip "Deliver"`
`4`	`4`	`What should be delivered?`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-# 🔔 HPS+FPGA - Assigment 1`
	`1`	`+# 🔔 Assessment 6`
`2`	`2`
`3`	`3`	`Você pode escolher entre um dos temas a seguir:`
`4`	`4`