@@ -87,6 +87,65 @@ struct TestDPPLSyclQueueInterface : public ::testing::Test
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{ }
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};
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+ TEST_F (TestDPPLSyclQueueInterface, CheckAreEq)
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+ {
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+ auto Q1 = DPPLQueueMgr_GetCurrentQueue ();
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+ auto Q2 = DPPLQueueMgr_GetCurrentQueue ();
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+ EXPECT_TRUE (DPPLQueue_AreEq (Q1, Q2));
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+
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+ auto nOclGPU = DPPLQueueMgr_GetNumQueues (DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_GPU);
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+ auto nOclCPU = DPPLQueueMgr_GetNumQueues (DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_CPU);
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+ {
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+ if (!nOclGPU)
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+ GTEST_SKIP_ (" No OpenCL GPUs available.\n " );
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+
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+ auto Def_Q = DPPLQueueMgr_SetAsDefaultQueue (
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+ DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_GPU,
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+ 0
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+ );
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+ auto OclGPU_Q0 = DPPLQueueMgr_PushQueue (
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+ DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_GPU,
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+ 0
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+ );
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+ auto OclGPU_Q1 = DPPLQueueMgr_PushQueue (
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+ DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_GPU,
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+ 0
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+ );
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+ EXPECT_TRUE (DPPLQueue_AreEq (Def_Q, OclGPU_Q0));
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+ EXPECT_TRUE (DPPLQueue_AreEq (Def_Q, OclGPU_Q1));
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+ EXPECT_TRUE (DPPLQueue_AreEq (OclGPU_Q0, OclGPU_Q1));
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+ DPPLQueue_Delete (Def_Q);
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+ DPPLQueue_Delete (OclGPU_Q0);
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+ DPPLQueue_Delete (OclGPU_Q1);
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+ DPPLQueueMgr_PopQueue ();
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+ DPPLQueueMgr_PopQueue ();
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+ }
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+
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+ {
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+ if (!nOclGPU || !nOclCPU)
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+ GTEST_SKIP_ (" OpenCL GPUs and CPU not available.\n " );
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+ auto GPU_Q = DPPLQueueMgr_PushQueue (
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+ DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_GPU,
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+ 0
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+ );
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+ auto CPU_Q = DPPLQueueMgr_PushQueue (
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+ DPPLSyclBEType::DPPL_OPENCL,
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+ DPPLSyclDeviceType::DPPL_CPU,
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+ 0
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+ );
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+ EXPECT_FALSE (DPPLQueue_AreEq (GPU_Q, CPU_Q));
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+ DPPLQueueMgr_PopQueue ();
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+ DPPLQueueMgr_PopQueue ();
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+ }
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+
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+ }
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+
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TEST_F (TestDPPLSyclQueueInterface, CheckGetBackend)
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{
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auto Q1 = DPPLQueueMgr_GetCurrentQueue ();
@@ -101,16 +160,19 @@ TEST_F (TestDPPLSyclQueueInterface, CheckGetBackend)
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auto Q = DPPLQueueMgr_PushQueue (DPPL_OPENCL, DPPL_GPU, 0 );
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EXPECT_TRUE (DPPLQueue_GetBackend (Q) == DPPL_OPENCL);
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DPPLQueue_Delete (Q);
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+ DPPLQueueMgr_PopQueue ();
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}
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if (DPPLQueueMgr_GetNumQueues (DPPL_OPENCL, DPPL_CPU)) {
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auto Q = DPPLQueueMgr_PushQueue (DPPL_OPENCL, DPPL_CPU, 0 );
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EXPECT_TRUE (DPPLQueue_GetBackend (Q) == DPPL_OPENCL);
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DPPLQueue_Delete (Q);
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+ DPPLQueueMgr_PopQueue ();
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}
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if (DPPLQueueMgr_GetNumQueues (DPPL_LEVEL_ZERO, DPPL_GPU)) {
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auto Q = DPPLQueueMgr_PushQueue (DPPL_LEVEL_ZERO, DPPL_GPU, 0 );
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EXPECT_TRUE (DPPLQueue_GetBackend (Q) == DPPL_LEVEL_ZERO);
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DPPLQueue_Delete (Q);
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+ DPPLQueueMgr_PopQueue ();
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}
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}
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@@ -128,20 +190,23 @@ TEST_F (TestDPPLSyclQueueInterface, CheckGetContext)
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ASSERT_TRUE (OclGpuCtx != nullptr );
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DPPLQueue_Delete (Q);
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DPPLContext_Delete (OclGpuCtx);
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+ DPPLQueueMgr_PopQueue ();
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}
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if (DPPLQueueMgr_GetNumQueues (DPPL_OPENCL, DPPL_CPU)) {
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auto Q = DPPLQueueMgr_PushQueue (DPPL_OPENCL, DPPL_CPU, 0 );
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auto OclCpuCtx = DPPLQueue_GetContext (Q);
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ASSERT_TRUE (OclCpuCtx != nullptr );
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DPPLQueue_Delete (Q);
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DPPLContext_Delete (OclCpuCtx);
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+ DPPLQueueMgr_PopQueue ();
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}
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if (DPPLQueueMgr_GetNumQueues (DPPL_LEVEL_ZERO, DPPL_GPU)) {
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auto Q = DPPLQueueMgr_PushQueue (DPPL_LEVEL_ZERO, DPPL_GPU, 0 );
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auto L0Ctx = DPPLQueue_GetContext (Q);
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ASSERT_TRUE (Ctx != nullptr );
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DPPLQueue_Delete (Q);
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DPPLContext_Delete (L0Ctx);
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+ DPPLQueueMgr_PopQueue ();
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}
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}
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@@ -160,6 +225,7 @@ TEST_F (TestDPPLSyclQueueInterface, CheckGetDevice)
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EXPECT_TRUE (DPPLDevice_IsGPU (OCLGPU_D));
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DPPLQueue_Delete (Q);
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DPPLDevice_Delete (OCLGPU_D);
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+ DPPLQueueMgr_PopQueue ();
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}
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if (DPPLQueueMgr_GetNumQueues (DPPL_OPENCL, DPPL_CPU)) {
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auto Q = DPPLQueueMgr_PushQueue (DPPL_OPENCL, DPPL_CPU, 0 );
@@ -168,6 +234,7 @@ TEST_F (TestDPPLSyclQueueInterface, CheckGetDevice)
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EXPECT_TRUE (DPPLDevice_IsCPU (OCLCPU_D));
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DPPLQueue_Delete (Q);
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DPPLDevice_Delete (OCLCPU_D);
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+ DPPLQueueMgr_PopQueue ();
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}
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if (DPPLQueueMgr_GetNumQueues (DPPL_LEVEL_ZERO, DPPL_GPU)) {
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auto Q = DPPLQueueMgr_PushQueue (DPPL_LEVEL_ZERO, DPPL_GPU, 0 );
@@ -176,6 +243,7 @@ TEST_F (TestDPPLSyclQueueInterface, CheckGetDevice)
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EXPECT_TRUE (DPPLDevice_IsGPU (L0GPU_D));
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DPPLQueue_Delete (Q);
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DPPLDevice_Delete (L0GPU_D);
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+ DPPLQueueMgr_PopQueue ();
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}
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}
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