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1 parent 51fc1e6 commit a4b5b1fCopy full SHA for a4b5b1f
dpctl/tests/test_sycl_usm.py
@@ -28,17 +28,19 @@
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import dpctl._memory
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import numpy as np
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+
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class Dummy(MemoryUSMShared):
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"""
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Class that exposes `__sycl_usm_array_interface__` with
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SYCL context for sycl object, instead of Sycl queue.
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@property
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def __sycl_usm_array_interface(self):
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iface = super().__sycl_usm_array_interface__
- iface['syclob'] = iface['syclobj'].get_sycl_context()
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+ iface["syclob"] = iface["syclobj"].get_sycl_context()
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return iface
-
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class TestMemory(unittest.TestCase):
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@unittest.skipUnless(
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