1+ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12; RUN: llc -O3 -mcpu=mips32r2 -mtriple=mipsel-linux-gnu < %s -o - \
23; RUN: | FileCheck %s --check-prefixes=MIPS32R2
34; RUN: llc -O3 -mcpu=mips64r2 -mtriple=mips64el < %s \
@@ -9,7 +10,14 @@ define i32 @or_and_shl(i32 %a, i32 %b) {
910; MIPS32R2-NEXT: ins $4, $5, 31, 1
1011; MIPS32R2-NEXT: jr $ra
1112; MIPS32R2-NEXT: move $2, $4
12-
13+ ;
14+ ; MIPS64R2-LABEL: or_and_shl:
15+ ; MIPS64R2: # %bb.0: # %entry
16+ ; MIPS64R2-NEXT: sll $2, $4, 0
17+ ; MIPS64R2-NEXT: sll $1, $5, 0
18+ ; MIPS64R2-NEXT: ins $2, $1, 31, 1
19+ ; MIPS64R2-NEXT: jr $ra
20+ ; MIPS64R2-NEXT: nop
1321entry:
1422 %shl = shl i32 %b , 31
1523 %and = and i32 %a , 2147483647
@@ -23,7 +31,14 @@ define i32 @or_shl_and(i32 %a, i32 %b) {
2331; MIPS32R2-NEXT: ins $4, $5, 31, 1
2432; MIPS32R2-NEXT: jr $ra
2533; MIPS32R2-NEXT: move $2, $4
26-
34+ ;
35+ ; MIPS64R2-LABEL: or_shl_and:
36+ ; MIPS64R2: # %bb.0: # %entry
37+ ; MIPS64R2-NEXT: sll $2, $4, 0
38+ ; MIPS64R2-NEXT: sll $1, $5, 0
39+ ; MIPS64R2-NEXT: ins $2, $1, 31, 1
40+ ; MIPS64R2-NEXT: jr $ra
41+ ; MIPS64R2-NEXT: nop
2742entry:
2843 %shl = shl i32 %b , 31
2944 %and = and i32 %a , 2147483647
@@ -32,12 +47,20 @@ entry:
3247}
3348
3449define i64 @dinsm (i64 %a , i64 %b ) {
50+ ; MIPS32R2-LABEL: dinsm:
51+ ; MIPS32R2: # %bb.0: # %entry
52+ ; MIPS32R2-NEXT: ins $4, $6, 17, 15
53+ ; MIPS32R2-NEXT: srl $1, $6, 15
54+ ; MIPS32R2-NEXT: sll $2, $7, 17
55+ ; MIPS32R2-NEXT: or $3, $2, $1
56+ ; MIPS32R2-NEXT: jr $ra
57+ ; MIPS32R2-NEXT: move $2, $4
58+ ;
3559; MIPS64R2-LABEL: dinsm:
3660; MIPS64R2: # %bb.0: # %entry
3761; MIPS64R2-NEXT: dinsm $4, $5, 17, 47
3862; MIPS64R2-NEXT: jr $ra
3963; MIPS64R2-NEXT: move $2, $4
40-
4164entry:
4265 %shl = shl i64 %b , 17
4366 %and = and i64 %a , 131071
@@ -46,12 +69,18 @@ entry:
4669}
4770
4871define i64 @dinsu (i64 %a , i64 %b ) {
72+ ; MIPS32R2-LABEL: dinsu:
73+ ; MIPS32R2: # %bb.0: # %entry
74+ ; MIPS32R2-NEXT: ins $5, $6, 3, 29
75+ ; MIPS32R2-NEXT: move $2, $4
76+ ; MIPS32R2-NEXT: jr $ra
77+ ; MIPS32R2-NEXT: move $3, $5
78+ ;
4979; MIPS64R2-LABEL: dinsu:
5080; MIPS64R2: # %bb.0: # %entry
5181; MIPS64R2-NEXT: dinsu $4, $5, 35, 29
5282; MIPS64R2-NEXT: jr $ra
5383; MIPS64R2-NEXT: move $2, $4
54-
5584entry:
5685 %shl = shl i64 %b , 35
5786 %and = and i64 %a , 34359738367
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