Constants are local aliases for values introduced with the const keyword. They
are stronger than text macros by having an associated type and hence bit width:
fsm baz {
const u32 MAGIC = 32'habcd_0123;
...
}
Constants are emitted in the generated Verilog as localparam decalartions:
module baz (
input wire clk,
input wire rst_n,
...
);
localparam [31:0] MAGIC = 32'habcd0123;
...
endmoduleNote however, that even though const declarations are emitted in the target
language, the compiler will inline the value of const declarations where it
deems necessary, especially in declarations of signals.
Entities can declare typed parameters, introduced with the param keyword.
Parameters must have a default value, which can be overridden at instantiation
time:
fsm foo {
param u8 MARKER = 8'h7f;
}
network bar {
foo_i = new foo(MARKER = 8'hf7);
}
Alogic performs parameter specialization, meaning the compiler will emit
specific implementations of a parametrized module, based on the particular
parameter values it is instantiated with. This means that Verilog modules output
by the Alogic compiler will never contain parameter declarations. Specialized
parameters are emitted as localparam declarations in the output Verilog. For
the above example, the compiler would emit the following specialization of
entity foo:
module foo__MARKER_247 (
input wire clk,
input wire rst_n,
...
);
localparam [7:0] MARKER = 8'd247;
...
endmoduleOne benefit of parameter specialization is that as opposed to Verilog, port
declarations in Alogic can depend on const values:
fsm bar {
param u32 WIDTH_L2 = 8;
const u32 WIDTH = 1<<WIDTH_L2;
in sync uint(WIDTH) p_in;
out sync uint(2*WIDTH) p_out;
...
}
Further benefits of parameter specialization include the possibility of further compile time optimization of the specialized entities and elimination of Verilog instance based code coverage holes arising from use of constant parameter values in expressions.