[CodeGen] Use Register or MCRegister. NFC

Author: topperc

llvm/include/llvm/CodeGen/DetectDeadLanes.h

@@ -37,6 +37,7 @@ namespace llvm {
 class MachineInstr;
 class MachineOperand;
 class MachineRegisterInfo;
+class Register;
 class TargetRegisterInfo;
 
 class DeadLaneDetector {
@@ -92,8 +93,8 @@ class DeadLaneDetector {
                                 const MachineOperand &MO) const;
 
 private:
-  LaneBitmask determineInitialDefinedLanes(unsigned Reg);
-  LaneBitmask determineInitialUsedLanes(unsigned Reg);
+  LaneBitmask determineInitialDefinedLanes(Register Reg);
+  LaneBitmask determineInitialUsedLanes(Register Reg);
 
   const MachineRegisterInfo *MRI;
   const TargetRegisterInfo *TRI;

llvm/include/llvm/CodeGen/ExecutionDomainFix.h

@@ -156,7 +156,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
   /// Translate TRI register number to a list of indices into our smaller tables
   /// of interesting registers.
   iterator_range<SmallVectorImpl<int>::const_iterator>
-  regIndices(unsigned Reg) const;
+  regIndices(MCRegister Reg) const;
 
   /// DomainValue allocation.
   DomainValue *alloc(int domain = -1);

llvm/include/llvm/CodeGen/LiveRangeCalc.h

@@ -147,7 +147,7 @@ class LiveRangeCalc {
   ///
   /// PhysReg, when set, is used to verify live-in lists on basic blocks.
   bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
-                        unsigned PhysReg, ArrayRef<SlotIndex> Undefs);
+                        Register PhysReg, ArrayRef<SlotIndex> Undefs);
 
   /// updateSSA - Compute the values that will be live in to all requested
   /// blocks in LiveIn.  Create PHI-def values as required to preserve SSA form.
@@ -204,7 +204,7 @@ class LiveRangeCalc {
   /// inserted as required to preserve SSA form.
   ///
   /// PhysReg, when set, is used to verify live-in lists on basic blocks.
-  void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
+  void extend(LiveRange &LR, SlotIndex Use, Register PhysReg,
               ArrayRef<SlotIndex> Undefs);
 
   //===--------------------------------------------------------------------===//

llvm/include/llvm/CodeGen/LiveRegMatrix.h

@@ -56,7 +56,7 @@ class LiveRegMatrix {
 
   // Cached register mask interference info.
   unsigned RegMaskTag = 0;
-  unsigned RegMaskVirtReg = 0;
+  Register RegMaskVirtReg;
   BitVector RegMaskUsable;
 
   LiveRegMatrix()

llvm/include/llvm/CodeGen/LiveVariables.h

@@ -135,7 +135,7 @@ class LiveVariables {
   // register references are presumed dead across basic blocks.
   std::vector<MachineInstr *> PhysRegUse;
 
-  std::vector<SmallVector<unsigned, 4>> PHIVarInfo;
+  std::vector<SmallVector<Register, 4>> PHIVarInfo;
 
   // DistanceMap - Keep track the distance of a MI from the start of the
   // current basic block.

llvm/lib/CodeGen/AllocationOrder.cpp

@@ -26,7 +26,7 @@ using namespace llvm;
 #define DEBUG_TYPE "regalloc"
 
 // Compare VirtRegMap::getRegAllocPref().
-AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
+AllocationOrder AllocationOrder::create(Register VirtReg, const VirtRegMap &VRM,
                                         const RegisterClassInfo &RegClassInfo,
                                         const LiveRegMatrix *Matrix) {
   const MachineFunction &MF = VRM.getMachineFunction();

llvm/lib/CodeGen/AllocationOrder.h

@@ -81,7 +81,7 @@ class LLVM_LIBRARY_VISIBILITY AllocationOrder {
   /// @param VirtReg      Virtual register to allocate for.
   /// @param VRM          Virtual register map for function.
   /// @param RegClassInfo Information about reserved and allocatable registers.
-  static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
+  static AllocationOrder create(Register VirtReg, const VirtRegMap &VRM,
                                 const RegisterClassInfo &RegClassInfo,
                                 const LiveRegMatrix *Matrix);
 

llvm/lib/CodeGen/DetectDeadLanes.cpp

@@ -265,7 +265,7 @@ LaneBitmask DeadLaneDetector::transferDefinedLanes(
   return DefinedLanes;
 }
 
-LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(unsigned Reg) {
+LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(Register Reg) {
   // Live-In or unused registers have no definition but are considered fully
   // defined.
   if (!MRI->hasOneDef(Reg))
@@ -330,7 +330,7 @@ LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(unsigned Reg) {
   return MRI->getMaxLaneMaskForVReg(Reg);
 }
 
-LaneBitmask DeadLaneDetector::determineInitialUsedLanes(unsigned Reg) {
+LaneBitmask DeadLaneDetector::determineInitialUsedLanes(Register Reg) {
   LaneBitmask UsedLanes = LaneBitmask::getNone();
   for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
     if (!MO.readsReg())

llvm/lib/CodeGen/ExecutionDomainFix.cpp

@@ -16,7 +16,7 @@ using namespace llvm;
 #define DEBUG_TYPE "execution-deps-fix"
 
 iterator_range<SmallVectorImpl<int>::const_iterator>
-ExecutionDomainFix::regIndices(unsigned Reg) const {
+ExecutionDomainFix::regIndices(MCRegister Reg) const {
   assert(Reg < AliasMap.size() && "Invalid register");
   const auto &Entry = AliasMap[Reg];
   return make_range(Entry.begin(), Entry.end());

llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

@@ -425,7 +425,7 @@ class StatepointState {
     }
   }
 
-  void insertReloadBefore(unsigned Reg, MachineBasicBlock::iterator It,
+  void insertReloadBefore(Register Reg, MachineBasicBlock::iterator It,
                           MachineBasicBlock *MBB) {
     const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
     int FI = RegToSlotIdx[Reg];