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Geetha sowjanyadavem330
Geetha sowjanya
authored and
davem330
committed
octeontx2-af: cn10k: mcs: Add mailboxes for port related operations
There are set of configurations to be done at MCS port level like bringing port out of reset, making port as operational or bypass. This patch adds all the port related mailbox message handlers so that AF consumers can use them. Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Vamsi Attunuru <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/marvell/octeontx2/af/mbox.h

Lines changed: 108 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -293,9 +293,21 @@ M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
293293
M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
294294
msg_rsp) \
295295
M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
296-
nix_bandprof_get_hwinfo_rsp)
297-
298-
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
296+
nix_bandprof_get_hwinfo_rsp) \
297+
/* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
298+
M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
299+
msg_rsp) \
300+
M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
301+
M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
302+
M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
303+
M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
304+
M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
305+
mcs_port_cfg_get_rsp) \
306+
M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
307+
mcs_custom_tag_cfg_get_req, \
308+
mcs_custom_tag_cfg_get_rsp)
309+
310+
/* Messages initiated by AF (range 0xC00 - 0xEFF) */
299311
#define MBOX_UP_CGX_MESSAGES \
300312
M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
301313

@@ -1657,4 +1669,97 @@ enum cgx_af_status {
16571669
LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
16581670
};
16591671

1672+
enum mcs_direction {
1673+
MCS_RX,
1674+
MCS_TX,
1675+
};
1676+
1677+
struct mcs_hw_info {
1678+
struct mbox_msghdr hdr;
1679+
u8 num_mcs_blks; /* Number of MCS blocks */
1680+
u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
1681+
u8 secy_entries; /* RX/TX SECY entries per mcs block */
1682+
u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
1683+
u8 sa_entries; /* PN table entries = SA entries */
1684+
u64 rsvd[16];
1685+
};
1686+
1687+
struct mcs_set_active_lmac {
1688+
struct mbox_msghdr hdr;
1689+
u32 lmac_bmap; /* bitmap of active lmac per mcs block */
1690+
u8 mcs_id;
1691+
u16 chan_base; /* MCS channel base */
1692+
u64 rsvd;
1693+
};
1694+
1695+
struct mcs_set_lmac_mode {
1696+
struct mbox_msghdr hdr;
1697+
u8 mode; /* 1:Bypass 0:Operational */
1698+
u8 lmac_id;
1699+
u8 mcs_id;
1700+
u64 rsvd;
1701+
};
1702+
1703+
struct mcs_port_reset_req {
1704+
struct mbox_msghdr hdr;
1705+
u8 reset;
1706+
u8 mcs_id;
1707+
u8 port_id;
1708+
u64 rsvd;
1709+
};
1710+
1711+
struct mcs_port_cfg_set_req {
1712+
struct mbox_msghdr hdr;
1713+
u8 cstm_tag_rel_mode_sel;
1714+
u8 custom_hdr_enb;
1715+
u8 fifo_skid;
1716+
u8 port_mode;
1717+
u8 port_id;
1718+
u8 mcs_id;
1719+
u64 rsvd;
1720+
};
1721+
1722+
struct mcs_port_cfg_get_req {
1723+
struct mbox_msghdr hdr;
1724+
u8 port_id;
1725+
u8 mcs_id;
1726+
u64 rsvd;
1727+
};
1728+
1729+
struct mcs_port_cfg_get_rsp {
1730+
struct mbox_msghdr hdr;
1731+
u8 cstm_tag_rel_mode_sel;
1732+
u8 custom_hdr_enb;
1733+
u8 fifo_skid;
1734+
u8 port_mode;
1735+
u8 port_id;
1736+
u8 mcs_id;
1737+
u64 rsvd;
1738+
};
1739+
1740+
struct mcs_custom_tag_cfg_get_req {
1741+
struct mbox_msghdr hdr;
1742+
u8 mcs_id;
1743+
u8 dir;
1744+
u64 rsvd;
1745+
};
1746+
1747+
struct mcs_custom_tag_cfg_get_rsp {
1748+
struct mbox_msghdr hdr;
1749+
u16 cstm_etype[8];
1750+
u8 cstm_indx[8];
1751+
u8 cstm_etype_en;
1752+
u8 mcs_id;
1753+
u8 dir;
1754+
u64 rsvd;
1755+
};
1756+
1757+
/* MCS mailbox error codes
1758+
* Range 1201 - 1300.
1759+
*/
1760+
enum mcs_af_status {
1761+
MCS_AF_ERR_INVALID_MCSID = -1201,
1762+
MCS_AF_ERR_NOT_MAPPED = -1202,
1763+
};
1764+
16601765
#endif /* MBOX_H */

‎drivers/net/ethernet/marvell/octeontx2/af/mcs.c

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,100 @@ struct mcs *mcs_get_pdata(int mcs_id)
107107
return NULL;
108108
}
109109

110+
void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req)
111+
{
112+
u64 val = 0;
113+
114+
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id),
115+
req->port_mode & MCS_PORT_MODE_MASK);
116+
117+
req->cstm_tag_rel_mode_sel &= 0x3;
118+
119+
if (mcs->hw->mcs_blks > 1) {
120+
req->fifo_skid &= MCS_PORT_FIFO_SKID_MASK;
121+
val = (u32)req->fifo_skid << 0x10;
122+
val |= req->fifo_skid;
123+
mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val);
124+
mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id),
125+
req->cstm_tag_rel_mode_sel);
126+
val = mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION);
127+
128+
if (req->custom_hdr_enb)
129+
val |= BIT_ULL(req->port_id);
130+
else
131+
val &= ~BIT_ULL(req->port_id);
132+
133+
mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, val);
134+
} else {
135+
val = mcs_reg_read(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id));
136+
val |= (req->cstm_tag_rel_mode_sel << 2);
137+
mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val);
138+
}
139+
}
140+
141+
void mcs_get_port_cfg(struct mcs *mcs, struct mcs_port_cfg_get_req *req,
142+
struct mcs_port_cfg_get_rsp *rsp)
143+
{
144+
u64 reg = 0;
145+
146+
rsp->port_mode = mcs_reg_read(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id)) &
147+
MCS_PORT_MODE_MASK;
148+
149+
if (mcs->hw->mcs_blks > 1) {
150+
reg = MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id);
151+
rsp->fifo_skid = mcs_reg_read(mcs, reg) & MCS_PORT_FIFO_SKID_MASK;
152+
reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id);
153+
rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) & 0x3;
154+
if (mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION) & BIT_ULL(req->port_id))
155+
rsp->custom_hdr_enb = 1;
156+
} else {
157+
reg = MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id);
158+
rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) >> 2;
159+
}
160+
161+
rsp->port_id = req->port_id;
162+
rsp->mcs_id = req->mcs_id;
163+
}
164+
165+
void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *req,
166+
struct mcs_custom_tag_cfg_get_rsp *rsp)
167+
{
168+
u64 reg = 0, val = 0;
169+
u8 idx;
170+
171+
for (idx = 0; idx < MCS_MAX_CUSTOM_TAGS; idx++) {
172+
if (mcs->hw->mcs_blks > 1)
173+
reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(idx) :
174+
MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(idx);
175+
else
176+
reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_VLAN_CFGX(idx) :
177+
MCSX_PEX_TX_SLAVE_VLAN_CFGX(idx);
178+
179+
val = mcs_reg_read(mcs, reg);
180+
if (mcs->hw->mcs_blks > 1) {
181+
rsp->cstm_etype[idx] = val & GENMASK(15, 0);
182+
rsp->cstm_indx[idx] = (val >> 0x16) & 0x3;
183+
reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_ETYPE_ENABLE :
184+
MCSX_PEX_TX_SLAVE_ETYPE_ENABLE;
185+
rsp->cstm_etype_en = mcs_reg_read(mcs, reg) & 0xFF;
186+
} else {
187+
rsp->cstm_etype[idx] = (val >> 0x1) & GENMASK(15, 0);
188+
rsp->cstm_indx[idx] = (val >> 0x11) & 0x3;
189+
rsp->cstm_etype_en |= (val & 0x1) << idx;
190+
}
191+
}
192+
193+
rsp->mcs_id = req->mcs_id;
194+
rsp->dir = req->dir;
195+
}
196+
197+
void mcs_reset_port(struct mcs *mcs, u8 port_id, u8 reset)
198+
{
199+
u64 reg = MCSX_MCS_TOP_SLAVE_PORT_RESET(port_id);
200+
201+
mcs_reg_write(mcs, reg, reset & 0x1);
202+
}
203+
110204
/* Set lmac to bypass/operational mode */
111205
void mcs_set_lmac_mode(struct mcs *mcs, int lmac_id, u8 mode)
112206
{

‎drivers/net/ethernet/marvell/octeontx2/af/mcs.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,10 @@
1717

1818
#define MCS_ID_MASK 0x7
1919

20+
#define MCS_PORT_MODE_MASK 0x3
21+
#define MCS_PORT_FIFO_SKID_MASK 0x3F
22+
#define MCS_MAX_CUSTOM_TAGS 0x8
23+
2024
/* Reserved resources for default bypass entry */
2125
#define MCS_RSRC_RSVD_CNT 1
2226

@@ -79,6 +83,12 @@ int mcs_set_lmac_channels(int mcs_id, u16 base);
7983

8084
int mcs_install_flowid_bypass_entry(struct mcs *mcs);
8185
void mcs_set_lmac_mode(struct mcs *mcs, int lmac_id, u8 mode);
86+
void mcs_reset_port(struct mcs *mcs, u8 port_id, u8 reset);
87+
void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req);
88+
void mcs_get_port_cfg(struct mcs *mcs, struct mcs_port_cfg_get_req *req,
89+
struct mcs_port_cfg_get_rsp *rsp);
90+
void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *req,
91+
struct mcs_custom_tag_cfg_get_rsp *rsp);
8292

8393
/* CN10K-B APIs */
8494
void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs);

‎drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,15 @@
1111

1212
/* Registers */
1313
#define MCSX_IP_MODE 0x900c8ull
14+
#define MCSX_MCS_TOP_SLAVE_PORT_RESET(a) ({ \
15+
u64 offset; \
16+
\
17+
offset = 0x408ull; \
18+
if (mcs->hw->mcs_blks > 1) \
19+
offset = 0xa28ull; \
20+
offset += (a) * 0x8ull; \
21+
offset; })
22+
1423

1524
#define MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(a) ({ \
1625
u64 offset; \
@@ -29,6 +38,23 @@
2938
offset = 0x60000ull; \
3039
offset; })
3140

41+
#define MCSX_MIL_RX_LMACX_CFG(a) ({ \
42+
u64 offset; \
43+
\
44+
offset = 0x900a8ull; \
45+
if (mcs->hw->mcs_blks > 1) \
46+
offset = 0x700a8ull; \
47+
offset += (a) * 0x800ull; \
48+
offset; })
49+
50+
#define MCSX_HIL_GLOBAL ({ \
51+
u64 offset; \
52+
\
53+
offset = 0xc0000ull; \
54+
if (mcs->hw->mcs_blks > 1) \
55+
offset = 0xa0000ull; \
56+
offset; })
57+
3258
#define MCSX_LINK_LMACX_CFG(a) ({ \
3359
u64 offset; \
3460
\
@@ -61,6 +87,16 @@
6187
/* PEX registers */
6288
#define MCSX_PEX_RX_SLAVE_VLAN_CFGX(a) (0x3b58ull + (a) * 0x8ull)
6389
#define MCSX_PEX_TX_SLAVE_VLAN_CFGX(a) (0x46f8ull + (a) * 0x8ull)
90+
#define MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(a) (0x788ull + (a) * 0x8ull)
91+
#define MCSX_PEX_TX_SLAVE_PORT_CONFIG(a) (0x4738ull + (a) * 0x8ull)
92+
93+
#define MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION ({ \
94+
u64 offset; \
95+
\
96+
offset = 0x3b50ull; \
97+
if (mcs->hw->mcs_blks > 1) \
98+
offset = 0x4c0ull; \
99+
offset; })
64100

65101
/* CNF10K-B */
66102
#define MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(a) (0x4c8ull + (a) * 0x8ull)

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