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AngeloGioacchino Del Regnowens
AngeloGioacchino Del Regno
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wens
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clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
1 parent b7520e2 commit 0d36328

10 files changed

+1408
-0
lines changed

‎drivers/clk/mediatek/Kconfig

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,43 @@ config COMMON_CLK_MT6779_AUDSYS
259259
help
260260
This driver supports Mediatek MT6779 audsys clocks.
261261

262+
config COMMON_CLK_MT6795
263+
tristate "Clock driver for MediaTek MT6795"
264+
depends on ARCH_MEDIATEK || COMPILE_TEST
265+
select COMMON_CLK_MEDIATEK
266+
default ARCH_MEDIATEK
267+
help
268+
This driver supports MediaTek MT6795 basic clocks and clocks
269+
required for various peripherals found on MediaTek.
270+
271+
config COMMON_CLK_MT6795_MFGCFG
272+
tristate "Clock driver for MediaTek MT6795 mfgcfg"
273+
depends on COMMON_CLK_MT6795
274+
default COMMON_CLK_MT6795
275+
help
276+
This driver supports MediaTek MT6795 mfgcfg clocks.
277+
278+
config COMMON_CLK_MT6795_MMSYS
279+
tristate "Clock driver for MediaTek MT6795 mmsys"
280+
depends on COMMON_CLK_MT6795
281+
default COMMON_CLK_MT6795
282+
help
283+
This driver supports MediaTek MT6795 mmsys clocks.
284+
285+
config COMMON_CLK_MT6795_VDECSYS
286+
tristate "Clock driver for MediaTek MT6795 VDECSYS"
287+
depends on COMMON_CLK_MT6795
288+
default COMMON_CLK_MT6795
289+
help
290+
This driver supports MediaTek MT6795 vdecsys clocks.
291+
292+
config COMMON_CLK_MT6795_VENCSYS
293+
tristate "Clock driver for MediaTek MT6795 VENCSYS"
294+
depends on COMMON_CLK_MT6795
295+
default COMMON_CLK_MT6795
296+
help
297+
This driver supports MediaTek MT6795 vencsys clocks.
298+
262299
config COMMON_CLK_MT6797
263300
bool "Clock driver for MediaTek MT6797"
264301
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,12 @@ obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
1717
obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
1818
obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
1919
obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
20+
obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \
21+
clk-mt6795-pericfg.o clk-mt6795-topckgen.o
22+
obj-$(CONFIG_COMMON_CLK_MT6795_MFGCFG) += clk-mt6795-mfg.o
23+
obj-$(CONFIG_COMMON_CLK_MT6795_MMSYS) += clk-mt6795-mm.o
24+
obj-$(CONFIG_COMMON_CLK_MT6795_VDECSYS) += clk-mt6795-vdecsys.o
25+
obj-$(CONFIG_COMMON_CLK_MT6795_VENCSYS) += clk-mt6795-vencsys.o
2026
obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
2127
obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
2228
obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o

‎drivers/clk/mediatek/clk-mt6795-apmixedsys.c

Lines changed: 157 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,157 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (c) 2022 Collabora Ltd.
4+
* Author: AngeloGioacchino Del Regno <[email protected]>
5+
*/
6+
7+
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
8+
#include <linux/module.h>
9+
#include <linux/platform_device.h>
10+
#include "clk-mtk.h"
11+
#include "clk-pll.h"
12+
13+
#define REG_REF2USB 0x8
14+
#define REG_AP_PLL_CON7 0x1c
15+
#define MD1_MTCMOS_OFF BIT(0)
16+
#define MD1_MEM_OFF BIT(1)
17+
#define MD1_CLK_OFF BIT(4)
18+
#define MD1_ISO_OFF BIT(8)
19+
20+
#define MT6795_PLL_FMAX (3000UL * MHZ)
21+
#define MT6795_CON0_EN BIT(0)
22+
#define MT6795_CON0_RST_BAR BIT(24)
23+
24+
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
25+
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
26+
.id = _id, \
27+
.name = _name, \
28+
.reg = _reg, \
29+
.pwr_reg = _pwr_reg, \
30+
.en_mask = MT6795_CON0_EN | _en_mask, \
31+
.flags = _flags, \
32+
.rst_bar_mask = MT6795_CON0_RST_BAR, \
33+
.fmax = MT6795_PLL_FMAX, \
34+
.pcwbits = _pcwbits, \
35+
.pd_reg = _pd_reg, \
36+
.pd_shift = _pd_shift, \
37+
.tuner_reg = _tuner_reg, \
38+
.pcw_reg = _pcw_reg, \
39+
.pcw_shift = _pcw_shift, \
40+
.div_table = NULL, \
41+
.pll_en_bit = 0, \
42+
}
43+
44+
static const struct mtk_pll_data plls[] = {
45+
PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
46+
21, 0x204, 24, 0x0, 0x204, 0),
47+
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
48+
21, 0x220, 4, 0x0, 0x224, 0),
49+
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
50+
7, 0x230, 4, 0x0, 0x234, 14),
51+
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
52+
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
53+
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
54+
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
55+
PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
56+
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
57+
PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
58+
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
59+
};
60+
61+
static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
62+
{
63+
void __iomem *reg = base + REG_AP_PLL_CON7;
64+
65+
/* Turn on MD1 internal clock */
66+
writel(readl(reg) & ~MD1_CLK_OFF, reg);
67+
68+
/* Unlock MD1's MTCMOS power path */
69+
writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);
70+
71+
/* Turn on ISO */
72+
writel(readl(reg) & ~MD1_ISO_OFF, reg);
73+
74+
/* Turn on memory */
75+
writel(readl(reg) & ~MD1_MEM_OFF, reg);
76+
}
77+
78+
static const struct of_device_id of_match_clk_mt6795_apmixed[] = {
79+
{ .compatible = "mediatek,mt6795-apmixedsys" },
80+
{ /* sentinel */ }
81+
};
82+
83+
static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
84+
{
85+
struct clk_hw_onecell_data *clk_data;
86+
struct device *dev = &pdev->dev;
87+
struct device_node *node = dev->of_node;
88+
void __iomem *base;
89+
struct clk_hw *hw;
90+
int ret;
91+
92+
base = devm_platform_ioremap_resource(pdev, 0);
93+
if (IS_ERR(base))
94+
return PTR_ERR(base);
95+
96+
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
97+
if (!clk_data)
98+
return -ENOMEM;
99+
100+
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
101+
if (ret)
102+
goto free_clk_data;
103+
104+
hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB);
105+
if (IS_ERR(hw)) {
106+
ret = PTR_ERR(hw);
107+
dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret);
108+
goto unregister_plls;
109+
}
110+
clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
111+
112+
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
113+
if (ret) {
114+
dev_err(dev, "Cannot register clock provider: %d\n", ret);
115+
goto unregister_ref2usb;
116+
}
117+
118+
/* Setup MD1 to avoid random crashes */
119+
dev_dbg(dev, "Performing initial setup for MD1\n");
120+
clk_mt6795_apmixed_setup_md1(base);
121+
122+
return 0;
123+
124+
unregister_ref2usb:
125+
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
126+
unregister_plls:
127+
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
128+
free_clk_data:
129+
mtk_free_clk_data(clk_data);
130+
return ret;
131+
}
132+
133+
static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
134+
{
135+
struct device_node *node = pdev->dev.of_node;
136+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
137+
138+
of_clk_del_provider(node);
139+
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
140+
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
141+
mtk_free_clk_data(clk_data);
142+
143+
return 0;
144+
}
145+
146+
static struct platform_driver clk_mt6795_apmixed_drv = {
147+
.probe = clk_mt6795_apmixed_probe,
148+
.remove = clk_mt6795_apmixed_remove,
149+
.driver = {
150+
.name = "clk-mt6795-apmixed",
151+
.of_match_table = of_match_clk_mt6795_apmixed,
152+
},
153+
};
154+
module_platform_driver(clk_mt6795_apmixed_drv);
155+
156+
MODULE_DESCRIPTION("MediaTek MT6795 apmixed clocks driver");
157+
MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt6795-infracfg.c

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,151 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (c) 2022 Collabora Ltd.
4+
* Author: AngeloGioacchino Del Regno <[email protected]>
5+
*/
6+
7+
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
8+
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
9+
#include <linux/module.h>
10+
#include <linux/platform_device.h>
11+
#include "clk-cpumux.h"
12+
#include "clk-gate.h"
13+
#include "clk-mtk.h"
14+
#include "reset.h"
15+
16+
#define GATE_ICG(_id, _name, _parent, _shift) \
17+
GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
18+
_shift, &mtk_clk_gate_ops_no_setclr)
19+
20+
static const struct mtk_gate_regs infra_cg_regs = {
21+
.set_ofs = 0x0040,
22+
.clr_ofs = 0x0044,
23+
.sta_ofs = 0x0048,
24+
};
25+
26+
static const char * const ca53_c0_parents[] = {
27+
"clk26m",
28+
"armca53pll",
29+
"mainpll",
30+
"univpll"
31+
};
32+
33+
static const char * const ca53_c1_parents[] = {
34+
"clk26m",
35+
"armca53pll",
36+
"mainpll",
37+
"univpll"
38+
};
39+
40+
static const struct mtk_composite cpu_muxes[] = {
41+
MUX(CLK_INFRA_CA53_C0_SEL, "infra_ca53_c0_sel", ca53_c0_parents, 0x00, 0, 2),
42+
MUX(CLK_INFRA_CA53_C1_SEL, "infra_ca53_c1_sel", ca53_c1_parents, 0x00, 2, 2),
43+
};
44+
45+
static const struct mtk_gate infra_gates[] = {
46+
GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
47+
GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
48+
GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
49+
GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
50+
GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
51+
GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
52+
GATE_ICG(CLK_INFRA_MD1MCU, "infra_md1mcu", "clk26m", 9),
53+
GATE_ICG(CLK_INFRA_MD1BUS, "infra_md1bus", "axi_sel", 10),
54+
GATE_ICG(CLK_INFRA_MD1DBB, "infra_dbb", "axi_sel", 11),
55+
GATE_ICG(CLK_INFRA_DEVICE_APC, "infra_devapc", "clk26m", 12),
56+
GATE_ICG(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 13),
57+
GATE_ICG(CLK_INFRA_MD1LTE, "infra_md1lte", "axi_sel", 14),
58+
GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
59+
GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
60+
};
61+
62+
static u16 infra_ao_rst_ofs[] = { 0x30, 0x34 };
63+
64+
static u16 infra_ao_idx_map[] = {
65+
[MT6795_INFRA_RST0_SCPSYS_RST] = 0 * RST_NR_PER_BANK + 5,
66+
[MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,
67+
[MT6795_INFRA_RST1_MIPI_DSI_RST] = 1 * RST_NR_PER_BANK + 4,
68+
[MT6795_INFRA_RST1_MIPI_CSI_RST] = 1 * RST_NR_PER_BANK + 7,
69+
[MT6795_INFRA_RST1_MM_IOMMU_RST] = 1 * RST_NR_PER_BANK + 15,
70+
};
71+
72+
static const struct mtk_clk_rst_desc clk_rst_desc = {
73+
.version = MTK_RST_SET_CLR,
74+
.rst_bank_ofs = infra_ao_rst_ofs,
75+
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
76+
.rst_idx_map = infra_ao_idx_map,
77+
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
78+
};
79+
80+
static const struct of_device_id of_match_clk_mt6795_infracfg[] = {
81+
{ .compatible = "mediatek,mt6795-infracfg" },
82+
{ /* sentinel */ }
83+
};
84+
85+
static int clk_mt6795_infracfg_probe(struct platform_device *pdev)
86+
{
87+
struct clk_hw_onecell_data *clk_data;
88+
struct device_node *node = pdev->dev.of_node;
89+
void __iomem *base;
90+
int ret;
91+
92+
base = devm_platform_ioremap_resource(pdev, 0);
93+
if (IS_ERR(base))
94+
return PTR_ERR(base);
95+
96+
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
97+
if (!clk_data)
98+
return -ENOMEM;
99+
100+
ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
101+
if (ret)
102+
goto free_clk_data;
103+
104+
ret = mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), clk_data);
105+
if (ret)
106+
goto free_clk_data;
107+
108+
ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
109+
if (ret)
110+
goto unregister_gates;
111+
112+
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
113+
if (ret)
114+
goto unregister_cpumuxes;
115+
116+
return 0;
117+
118+
unregister_cpumuxes:
119+
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
120+
unregister_gates:
121+
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
122+
free_clk_data:
123+
mtk_free_clk_data(clk_data);
124+
return ret;
125+
}
126+
127+
static int clk_mt6795_infracfg_remove(struct platform_device *pdev)
128+
{
129+
struct device_node *node = pdev->dev.of_node;
130+
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
131+
132+
of_clk_del_provider(node);
133+
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
134+
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
135+
mtk_free_clk_data(clk_data);
136+
137+
return 0;
138+
}
139+
140+
static struct platform_driver clk_mt6795_infracfg_drv = {
141+
.driver = {
142+
.name = "clk-mt6795-infracfg",
143+
.of_match_table = of_match_clk_mt6795_infracfg,
144+
},
145+
.probe = clk_mt6795_infracfg_probe,
146+
.remove = clk_mt6795_infracfg_remove,
147+
};
148+
module_platform_driver(clk_mt6795_infracfg_drv);
149+
150+
MODULE_DESCRIPTION("MediaTek MT6795 infracfg clocks driver");
151+
MODULE_LICENSE("GPL");

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