@@ -378,6 +378,26 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
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.num_clks = ARRAY_SIZE (sdm845_rpmh_clocks ),
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};
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+ static struct clk_hw * sdm670_rpmh_clocks [] = {
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+ [RPMH_CXO_CLK ] = & sdm845_bi_tcxo .hw ,
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+ [RPMH_CXO_CLK_A ] = & sdm845_bi_tcxo_ao .hw ,
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+ [RPMH_LN_BB_CLK2 ] = & sdm845_ln_bb_clk2 .hw ,
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+ [RPMH_LN_BB_CLK2_A ] = & sdm845_ln_bb_clk2_ao .hw ,
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+ [RPMH_LN_BB_CLK3 ] = & sdm845_ln_bb_clk3 .hw ,
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+ [RPMH_LN_BB_CLK3_A ] = & sdm845_ln_bb_clk3_ao .hw ,
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+ [RPMH_RF_CLK1 ] = & sdm845_rf_clk1 .hw ,
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+ [RPMH_RF_CLK1_A ] = & sdm845_rf_clk1_ao .hw ,
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+ [RPMH_RF_CLK2 ] = & sdm845_rf_clk2 .hw ,
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+ [RPMH_RF_CLK2_A ] = & sdm845_rf_clk2_ao .hw ,
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+ [RPMH_IPA_CLK ] = & sdm845_ipa .hw ,
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+ [RPMH_CE_CLK ] = & sdm845_ce .hw ,
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+ };
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+
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+ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
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+ .clks = sdm670_rpmh_clocks ,
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+ .num_clks = ARRAY_SIZE (sdm670_rpmh_clocks ),
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+ };
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+
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DEFINE_CLK_RPMH_VRM (sdx55 , rf_clk1 , rf_clk1_ao , "rfclkd1" , 1 );
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DEFINE_CLK_RPMH_VRM (sdx55 , rf_clk2 , rf_clk2_ao , "rfclkd2" , 1 );
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DEFINE_CLK_RPMH_BCM (sdx55 , qpic_clk , "QP0" );
@@ -711,6 +731,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
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{ .compatible = "qcom,sc8180x-rpmh-clk" , .data = & clk_rpmh_sc8180x },
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{ .compatible = "qcom,sc8280xp-rpmh-clk" , .data = & clk_rpmh_sc8280xp },
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{ .compatible = "qcom,sdm845-rpmh-clk" , .data = & clk_rpmh_sdm845 },
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+ { .compatible = "qcom,sdm670-rpmh-clk" , .data = & clk_rpmh_sdm670 },
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{ .compatible = "qcom,sdx55-rpmh-clk" , .data = & clk_rpmh_sdx55 },
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{ .compatible = "qcom,sdx65-rpmh-clk" , .data = & clk_rpmh_sdx65 },
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{ .compatible = "qcom,sm6350-rpmh-clk" , .data = & clk_rpmh_sm6350 },
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