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torvaldstorvalds
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Merge tag 'drm-fixes-2022-08-26-1' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Weekly fixes, lots of amdgpu fixes mostly for IP blocks introduced in 6.0-rc1, otherwise vc4, nouveau fixes. gem: - Fix handle release leak nouveau: - Fix fencing when moving BO vc4: - HDMI fixes amdgpu: - GFX 11.0 fixes - PSP XGMI handling fixes - GFX9 fix for compute-only IPs - Drop duplicated function call - Fix warning due to missing header - NBIO 7.7 fixes - DCN 3.1.4 fixes - SDMA 6.0 fixes - SMU 13.0 fixes - Arcturus GPUVM page table fix - MMHUB 1.0 fix amdkfd: - GC 10.3.7 fix radeon: - Delayed work flush fix" * tag 'drm-fixes-2022-08-26-1' of git://anongit.freedesktop.org/drm/drm: (21 commits) drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly drm/amdgpu: add MGCG perfmon setting for gfx11 drm/amdkfd: Fix isa version for the GC 10.3.7 drm/amdgpu: Fix page table setup on Arcturus drm/amd/pm: update SMU 13.0.0 driver_if header drm/amdgpu: add sdma instance check for gfx11 CGCG drm/amd/display: enable PCON support for dcn314 drm/amdgpu: enable NBIO IP v7.7.0 Clock Gating drm/amdgpu: add NBIO IP v7.7.0 Clock Gating support drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0 nouveau: explicitly wait on the fence in nouveau_bo_move_m2mf drm/radeon: add a force flush to delay work when radeon drm/amd/display: Include missing header drm/amdgpu: Remove the additional kfd pre reset call for sriov drm/amdgpu: Check num_gfx_rings for gfx v9_0 rb setup. drm/amdgpu: fix hive reference leak when adding xgmi device drm/amdgpu: Move psp_xgmi_terminate call from amdgpu_xgmi_remove_device to psp_hw_fini drm/amdgpu: enable GFXOFF allow control for GC IP v11.0.1 drm/gem: Fix GEM handle release errors drm/vc4: hdmi: Rework power up ...
2 parents 3e5c673 + 100d0ae commit 78effb4

24 files changed

+206
-82
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2456,12 +2456,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
24562456
if (!hive->reset_domain ||
24572457
!amdgpu_reset_get_reset_domain(hive->reset_domain)) {
24582458
r = -ENOENT;
2459+
amdgpu_put_xgmi_hive(hive);
24592460
goto init_failed;
24602461
}
24612462

24622463
/* Drop the early temporary reset domain we created for device */
24632464
amdgpu_reset_put_reset_domain(adev->reset_domain);
24642465
adev->reset_domain = hive->reset_domain;
2466+
amdgpu_put_xgmi_hive(hive);
24652467
}
24662468
}
24672469

@@ -4413,8 +4415,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
44134415
retry:
44144416
amdgpu_amdkfd_pre_reset(adev);
44154417

4416-
amdgpu_amdkfd_pre_reset(adev);
4417-
44184418
if (from_hypervisor)
44194419
r = amdgpu_virt_request_full_gpu(adev, true);
44204420
else

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2641,6 +2641,9 @@ static int psp_hw_fini(void *handle)
26412641
psp_rap_terminate(psp);
26422642
psp_dtm_terminate(psp);
26432643
psp_hdcp_terminate(psp);
2644+
2645+
if (adev->gmc.xgmi.num_physical_nodes > 1)
2646+
psp_xgmi_terminate(psp);
26442647
}
26452648

26462649
psp_asd_terminate(psp);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -742,7 +742,7 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
742742
amdgpu_put_xgmi_hive(hive);
743743
}
744744

745-
return psp_xgmi_terminate(&adev->psp);
745+
return 0;
746746
}
747747

748748
static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,8 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
131131
bool all_hub, uint8_t dst_sel);
132132
static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);
133133
static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
134+
static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
135+
bool enable);
134136

135137
static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
136138
{
@@ -1139,6 +1141,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
11391141
.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
11401142
.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
11411143
.init_spm_golden = &gfx_v11_0_init_spm_golden_registers,
1144+
.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
11421145
};
11431146

11441147
static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
@@ -5182,9 +5185,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
51825185
data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
51835186
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
51845187

5185-
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
5186-
data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
5187-
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
5188+
/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
5189+
if (adev->sdma.num_instances > 1) {
5190+
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
5191+
data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
5192+
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
5193+
}
51885194
} else {
51895195
/* Program RLC_CGCG_CGLS_CTRL */
51905196
def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
@@ -5213,9 +5219,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
52135219
data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
52145220
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
52155221

5216-
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
5217-
data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
5218-
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
5222+
/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
5223+
if (adev->sdma.num_instances > 1) {
5224+
data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
5225+
data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
5226+
WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
5227+
}
52195228
}
52205229
}
52215230

@@ -5328,8 +5337,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
53285337
break;
53295338
case IP_VERSION(11, 0, 1):
53305339
gfx_v11_cntl_pg(adev, enable);
5331-
/* TODO: Enable this when GFXOFF is ready */
5332-
// amdgpu_gfx_off_ctrl(adev, enable);
5340+
amdgpu_gfx_off_ctrl(adev, enable);
53335341
break;
53345342
default:
53355343
break;

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2587,7 +2587,8 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
25872587

25882588
gfx_v9_0_tiling_mode_table_init(adev);
25892589

2590-
gfx_v9_0_setup_rb(adev);
2590+
if (adev->gfx.num_gfx_rings)
2591+
gfx_v9_0_setup_rb(adev);
25912592
gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
25922593
adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
25932594

‎drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
176176
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
177177
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
178178

179+
tmp = mmVM_L2_CNTL3_DEFAULT;
179180
if (adev->gmc.translate_further) {
180181
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
181182
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

‎drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -295,17 +295,25 @@ static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
295295
static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
296296
{
297297
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
298+
unsigned int num_level, block_size;
298299
uint32_t tmp;
299300
int i;
300301

302+
num_level = adev->vm_manager.num_level;
303+
block_size = adev->vm_manager.block_size;
304+
if (adev->gmc.translate_further)
305+
num_level -= 1;
306+
else
307+
block_size -= 9;
308+
301309
for (i = 0; i <= 14; i++) {
302310
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
303311
hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
304312
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
305313
ENABLE_CONTEXT, 1);
306314
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
307315
PAGE_TABLE_DEPTH,
308-
adev->vm_manager.num_level);
316+
num_level);
309317
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
310318
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
311319
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
@@ -323,7 +331,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
323331
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
324332
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
325333
PAGE_TABLE_BLOCK_SIZE,
326-
adev->vm_manager.block_size - 9);
334+
block_size);
327335
/* Send no-retry XNACK on fault to suppress VM fault storm. */
328336
tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
329337
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,

‎drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -247,6 +247,81 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
247247

248248
}
249249

250+
static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
251+
bool enable)
252+
{
253+
uint32_t def, data;
254+
255+
if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
256+
return;
257+
258+
def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
259+
if (enable) {
260+
data |= (BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
261+
BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
262+
BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
263+
BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
264+
BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
265+
BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
266+
} else {
267+
data &= ~(BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
268+
BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
269+
BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
270+
BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
271+
BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
272+
BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
273+
}
274+
275+
if (def != data)
276+
WREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL, data);
277+
}
278+
279+
static void nbio_v7_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
280+
bool enable)
281+
{
282+
uint32_t def, data;
283+
284+
if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
285+
return;
286+
287+
def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
288+
if (enable)
289+
data |= BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
290+
else
291+
data &= ~BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
292+
293+
if (def != data)
294+
WREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2, data);
295+
296+
def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1);
297+
if (enable) {
298+
data |= (BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
299+
BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
300+
} else {
301+
data &= ~(BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
302+
BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
303+
}
304+
305+
if (def != data)
306+
WREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1, data);
307+
}
308+
309+
static void nbio_v7_7_get_clockgating_state(struct amdgpu_device *adev,
310+
u64 *flags)
311+
{
312+
uint32_t data;
313+
314+
/* AMD_CG_SUPPORT_BIF_MGCG */
315+
data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
316+
if (data & BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
317+
*flags |= AMD_CG_SUPPORT_BIF_MGCG;
318+
319+
/* AMD_CG_SUPPORT_BIF_LS */
320+
data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
321+
if (data & BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
322+
*flags |= AMD_CG_SUPPORT_BIF_LS;
323+
}
324+
250325
const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
251326
.get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
252327
.get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
@@ -262,6 +337,9 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
262337
.enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
263338
.enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
264339
.ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
340+
.update_medium_grain_clock_gating = nbio_v7_7_update_medium_grain_clock_gating,
341+
.update_medium_grain_light_sleep = nbio_v7_7_update_medium_grain_light_sleep,
342+
.get_clockgating_state = nbio_v7_7_get_clockgating_state,
265343
.ih_control = nbio_v7_7_ih_control,
266344
.init_registers = nbio_v7_7_init_registers,
267345
};

‎drivers/gpu/drm/amd/amdgpu/soc21.c

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -494,6 +494,20 @@ static void soc21_pre_asic_init(struct amdgpu_device *adev)
494494
{
495495
}
496496

497+
static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
498+
bool enter)
499+
{
500+
if (enter)
501+
amdgpu_gfx_rlc_enter_safe_mode(adev);
502+
else
503+
amdgpu_gfx_rlc_exit_safe_mode(adev);
504+
505+
if (adev->gfx.funcs->update_perfmon_mgcg)
506+
adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
507+
508+
return 0;
509+
}
510+
497511
static const struct amdgpu_asic_funcs soc21_asic_funcs =
498512
{
499513
.read_disabled_bios = &soc21_read_disabled_bios,
@@ -513,6 +527,7 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs =
513527
.supports_baco = &amdgpu_dpm_is_baco_supported,
514528
.pre_asic_init = &soc21_pre_asic_init,
515529
.query_video_codecs = &soc21_query_video_codecs,
530+
.update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
516531
};
517532

518533
static int soc21_common_early_init(void *handle)
@@ -603,6 +618,8 @@ static int soc21_common_early_init(void *handle)
603618
AMD_CG_SUPPORT_ATHUB_MGCG |
604619
AMD_CG_SUPPORT_ATHUB_LS |
605620
AMD_CG_SUPPORT_IH_CG |
621+
AMD_CG_SUPPORT_BIF_MGCG |
622+
AMD_CG_SUPPORT_BIF_LS |
606623
AMD_CG_SUPPORT_VCN_MGCG |
607624
AMD_CG_SUPPORT_JPEG_MGCG;
608625
adev->pg_flags =
@@ -702,17 +719,14 @@ static int soc21_common_set_clockgating_state(void *handle,
702719
switch (adev->ip_versions[NBIO_HWIP][0]) {
703720
case IP_VERSION(4, 3, 0):
704721
case IP_VERSION(4, 3, 1):
722+
case IP_VERSION(7, 7, 0):
705723
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
706724
state == AMD_CG_STATE_GATE);
707725
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
708726
state == AMD_CG_STATE_GATE);
709727
adev->hdp.funcs->update_clock_gating(adev,
710728
state == AMD_CG_STATE_GATE);
711729
break;
712-
case IP_VERSION(7, 7, 0):
713-
adev->hdp.funcs->update_clock_gating(adev,
714-
state == AMD_CG_STATE_GATE);
715-
break;
716730
default:
717731
break;
718732
}

‎drivers/gpu/drm/amd/amdkfd/kfd_device.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -382,12 +382,8 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
382382
f2g = &gfx_v10_3_kfd2kgd;
383383
break;
384384
case IP_VERSION(10, 3, 6):
385-
gfx_target_version = 100306;
386-
if (!vf)
387-
f2g = &gfx_v10_3_kfd2kgd;
388-
break;
389385
case IP_VERSION(10, 3, 7):
390-
gfx_target_version = 100307;
386+
gfx_target_version = 100306;
391387
if (!vf)
392388
f2g = &gfx_v10_3_kfd2kgd;
393389
break;

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