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ichernevandersson
ichernev
authored and
andersson
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clk: qcom: Merge alt alpha plls for qcm2260, sm6115
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by: Iskren Chernev <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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4 files changed

+57
-82
lines changed

4 files changed

+57
-82
lines changed

‎drivers/clk/qcom/clk-alpha-pll.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,27 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
166166
[PLL_OFF_TEST_CTL] = 0x28,
167167
[PLL_OFF_TEST_CTL_U] = 0x2c,
168168
},
169+
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
170+
[PLL_OFF_L_VAL] = 0x04,
171+
[PLL_OFF_ALPHA_VAL] = 0x08,
172+
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
173+
[PLL_OFF_TEST_CTL] = 0x10,
174+
[PLL_OFF_TEST_CTL_U] = 0x14,
175+
[PLL_OFF_USER_CTL] = 0x18,
176+
[PLL_OFF_USER_CTL_U] = 0x1c,
177+
[PLL_OFF_CONFIG_CTL] = 0x20,
178+
[PLL_OFF_STATUS] = 0x24,
179+
},
180+
[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
181+
[PLL_OFF_L_VAL] = 0x04,
182+
[PLL_OFF_ALPHA_VAL] = 0x08,
183+
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
184+
[PLL_OFF_TEST_CTL] = 0x10,
185+
[PLL_OFF_TEST_CTL_U] = 0x14,
186+
[PLL_OFF_USER_CTL] = 0x18,
187+
[PLL_OFF_CONFIG_CTL] = 0x1C,
188+
[PLL_OFF_STATUS] = 0x20,
189+
},
169190
};
170191
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
171192

‎drivers/clk/qcom/clk-alpha-pll.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@ enum {
1919
CLK_ALPHA_PLL_TYPE_ZONDA,
2020
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
2121
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
22+
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
23+
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
2224
CLK_ALPHA_PLL_TYPE_MAX,
2325
};
2426

‎drivers/clk/qcom/gcc-qcm2290.c

Lines changed: 16 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -54,33 +54,9 @@ static const struct pll_vco spark_vco[] = {
5454
{ 750000000, 1500000000, 1 },
5555
};
5656

57-
static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
58-
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
59-
[PLL_OFF_L_VAL] = 0x04,
60-
[PLL_OFF_ALPHA_VAL] = 0x08,
61-
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
62-
[PLL_OFF_TEST_CTL] = 0x10,
63-
[PLL_OFF_TEST_CTL_U] = 0x14,
64-
[PLL_OFF_USER_CTL] = 0x18,
65-
[PLL_OFF_USER_CTL_U] = 0x1C,
66-
[PLL_OFF_CONFIG_CTL] = 0x20,
67-
[PLL_OFF_STATUS] = 0x24,
68-
},
69-
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
70-
[PLL_OFF_L_VAL] = 0x04,
71-
[PLL_OFF_ALPHA_VAL] = 0x08,
72-
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
73-
[PLL_OFF_TEST_CTL] = 0x10,
74-
[PLL_OFF_TEST_CTL_U] = 0x14,
75-
[PLL_OFF_USER_CTL] = 0x18,
76-
[PLL_OFF_CONFIG_CTL] = 0x1C,
77-
[PLL_OFF_STATUS] = 0x20,
78-
},
79-
};
80-
8157
static struct clk_alpha_pll gpll0 = {
8258
.offset = 0x0,
83-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
59+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
8460
.clkr = {
8561
.enable_reg = 0x79000,
8662
.enable_mask = BIT(0),
@@ -106,7 +82,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
10682
.post_div_table = post_div_table_gpll0_out_aux2,
10783
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
10884
.width = 4,
109-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
85+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
11086
.clkr.hw.init = &(struct clk_init_data){
11187
.name = "gpll0_out_aux2",
11288
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@@ -117,7 +93,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
11793

11894
static struct clk_alpha_pll gpll1 = {
11995
.offset = 0x1000,
120-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
96+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
12197
.clkr = {
12298
.enable_reg = 0x79000,
12399
.enable_mask = BIT(1),
@@ -147,7 +123,7 @@ static struct clk_alpha_pll gpll10 = {
147123
.offset = 0xa000,
148124
.vco_table = spark_vco,
149125
.num_vco = ARRAY_SIZE(spark_vco),
150-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
126+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
151127
.clkr = {
152128
.enable_reg = 0x79000,
153129
.enable_mask = BIT(10),
@@ -179,7 +155,7 @@ static struct clk_alpha_pll gpll11 = {
179155
.offset = 0xb000,
180156
.vco_table = default_vco,
181157
.num_vco = ARRAY_SIZE(default_vco),
182-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
158+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
183159
.flags = SUPPORTS_DYNAMIC_UPDATE,
184160
.clkr = {
185161
.enable_reg = 0x79000,
@@ -197,7 +173,7 @@ static struct clk_alpha_pll gpll11 = {
197173

198174
static struct clk_alpha_pll gpll3 = {
199175
.offset = 0x3000,
200-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
176+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
201177
.clkr = {
202178
.enable_reg = 0x79000,
203179
.enable_mask = BIT(3),
@@ -223,7 +199,7 @@ static struct clk_alpha_pll_postdiv gpll3_out_main = {
223199
.post_div_table = post_div_table_gpll3_out_main,
224200
.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main),
225201
.width = 4,
226-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
202+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
227203
.clkr.hw.init = &(struct clk_init_data){
228204
.name = "gpll3_out_main",
229205
.parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw },
@@ -234,7 +210,7 @@ static struct clk_alpha_pll_postdiv gpll3_out_main = {
234210

235211
static struct clk_alpha_pll gpll4 = {
236212
.offset = 0x4000,
237-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
213+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
238214
.clkr = {
239215
.enable_reg = 0x79000,
240216
.enable_mask = BIT(4),
@@ -251,7 +227,7 @@ static struct clk_alpha_pll gpll4 = {
251227

252228
static struct clk_alpha_pll gpll5 = {
253229
.offset = 0x5000,
254-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
230+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
255231
.clkr = {
256232
.enable_reg = 0x79000,
257233
.enable_mask = BIT(5),
@@ -268,7 +244,7 @@ static struct clk_alpha_pll gpll5 = {
268244

269245
static struct clk_alpha_pll gpll6 = {
270246
.offset = 0x6000,
271-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
247+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
272248
.clkr = {
273249
.enable_reg = 0x79000,
274250
.enable_mask = BIT(6),
@@ -294,7 +270,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
294270
.post_div_table = post_div_table_gpll6_out_main,
295271
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
296272
.width = 4,
297-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
273+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
298274
.clkr.hw.init = &(struct clk_init_data){
299275
.name = "gpll6_out_main",
300276
.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
@@ -305,7 +281,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
305281

306282
static struct clk_alpha_pll gpll7 = {
307283
.offset = 0x7000,
308-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
284+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
309285
.clkr = {
310286
.enable_reg = 0x79000,
311287
.enable_mask = BIT(7),
@@ -340,7 +316,7 @@ static struct clk_alpha_pll gpll8 = {
340316
.offset = 0x8000,
341317
.vco_table = default_vco,
342318
.num_vco = ARRAY_SIZE(default_vco),
343-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
319+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
344320
.flags = SUPPORTS_DYNAMIC_UPDATE,
345321
.clkr = {
346322
.enable_reg = 0x79000,
@@ -367,7 +343,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
367343
.post_div_table = post_div_table_gpll8_out_main,
368344
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
369345
.width = 4,
370-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
346+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
371347
.clkr.hw.init = &(struct clk_init_data){
372348
.name = "gpll8_out_main",
373349
.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
@@ -393,7 +369,7 @@ static struct clk_alpha_pll gpll9 = {
393369
.offset = 0x9000,
394370
.vco_table = brammo_vco,
395371
.num_vco = ARRAY_SIZE(brammo_vco),
396-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
372+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
397373
.clkr = {
398374
.enable_reg = 0x79000,
399375
.enable_mask = BIT(9),
@@ -419,7 +395,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
419395
.post_div_table = post_div_table_gpll9_out_main,
420396
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
421397
.width = 2,
422-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
398+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
423399
.clkr.hw.init = &(struct clk_init_data){
424400
.name = "gpll9_out_main",
425401
.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },

‎drivers/clk/qcom/gcc-sm6115.c

Lines changed: 18 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -53,35 +53,11 @@ static struct pll_vco gpll10_vco[] = {
5353
{ 750000000, 1500000000, 1 },
5454
};
5555

56-
static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
57-
[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
58-
[PLL_OFF_L_VAL] = 0x04,
59-
[PLL_OFF_ALPHA_VAL] = 0x08,
60-
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
61-
[PLL_OFF_TEST_CTL] = 0x10,
62-
[PLL_OFF_TEST_CTL_U] = 0x14,
63-
[PLL_OFF_USER_CTL] = 0x18,
64-
[PLL_OFF_USER_CTL_U] = 0x1c,
65-
[PLL_OFF_CONFIG_CTL] = 0x20,
66-
[PLL_OFF_STATUS] = 0x24,
67-
},
68-
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
69-
[PLL_OFF_L_VAL] = 0x04,
70-
[PLL_OFF_ALPHA_VAL] = 0x08,
71-
[PLL_OFF_ALPHA_VAL_U] = 0x0c,
72-
[PLL_OFF_TEST_CTL] = 0x10,
73-
[PLL_OFF_TEST_CTL_U] = 0x14,
74-
[PLL_OFF_USER_CTL] = 0x18,
75-
[PLL_OFF_CONFIG_CTL] = 0x1C,
76-
[PLL_OFF_STATUS] = 0x20,
77-
},
78-
};
79-
8056
static struct clk_alpha_pll gpll0 = {
8157
.offset = 0x0,
8258
.vco_table = default_vco,
8359
.num_vco = ARRAY_SIZE(default_vco),
84-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
60+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
8561
.clkr = {
8662
.enable_reg = 0x79000,
8763
.enable_mask = BIT(0),
@@ -107,7 +83,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
10783
.post_div_table = post_div_table_gpll0_out_aux2,
10884
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
10985
.width = 4,
110-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
86+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
11187
.clkr.hw.init = &(struct clk_init_data){
11288
.name = "gpll0_out_aux2",
11389
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@@ -127,7 +103,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_main = {
127103
.post_div_table = post_div_table_gpll0_out_main,
128104
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
129105
.width = 4,
130-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
106+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
131107
.clkr.hw.init = &(struct clk_init_data){
132108
.name = "gpll0_out_main",
133109
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
@@ -149,7 +125,7 @@ static struct clk_alpha_pll gpll10 = {
149125
.offset = 0xa000,
150126
.vco_table = gpll10_vco,
151127
.num_vco = ARRAY_SIZE(gpll10_vco),
152-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
128+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
153129
.clkr = {
154130
.enable_reg = 0x79000,
155131
.enable_mask = BIT(10),
@@ -175,7 +151,7 @@ static struct clk_alpha_pll_postdiv gpll10_out_main = {
175151
.post_div_table = post_div_table_gpll10_out_main,
176152
.num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
177153
.width = 4,
178-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
154+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
179155
.clkr.hw.init = &(struct clk_init_data){
180156
.name = "gpll10_out_main",
181157
.parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
@@ -201,7 +177,7 @@ static struct clk_alpha_pll gpll11 = {
201177
.vco_table = default_vco,
202178
.num_vco = ARRAY_SIZE(default_vco),
203179
.flags = SUPPORTS_DYNAMIC_UPDATE,
204-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
180+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
205181
.clkr = {
206182
.enable_reg = 0x79000,
207183
.enable_mask = BIT(11),
@@ -227,7 +203,7 @@ static struct clk_alpha_pll_postdiv gpll11_out_main = {
227203
.post_div_table = post_div_table_gpll11_out_main,
228204
.num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
229205
.width = 4,
230-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
206+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
231207
.clkr.hw.init = &(struct clk_init_data){
232208
.name = "gpll11_out_main",
233209
.parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
@@ -241,7 +217,7 @@ static struct clk_alpha_pll gpll3 = {
241217
.offset = 0x3000,
242218
.vco_table = default_vco,
243219
.num_vco = ARRAY_SIZE(default_vco),
244-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
220+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
245221
.clkr = {
246222
.enable_reg = 0x79000,
247223
.enable_mask = BIT(3),
@@ -260,7 +236,7 @@ static struct clk_alpha_pll gpll4 = {
260236
.offset = 0x4000,
261237
.vco_table = default_vco,
262238
.num_vco = ARRAY_SIZE(default_vco),
263-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
239+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
264240
.clkr = {
265241
.enable_reg = 0x79000,
266242
.enable_mask = BIT(4),
@@ -286,7 +262,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_main = {
286262
.post_div_table = post_div_table_gpll4_out_main,
287263
.num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
288264
.width = 4,
289-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
265+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
290266
.clkr.hw.init = &(struct clk_init_data){
291267
.name = "gpll4_out_main",
292268
.parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
@@ -299,7 +275,7 @@ static struct clk_alpha_pll gpll6 = {
299275
.offset = 0x6000,
300276
.vco_table = default_vco,
301277
.num_vco = ARRAY_SIZE(default_vco),
302-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
278+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
303279
.clkr = {
304280
.enable_reg = 0x79000,
305281
.enable_mask = BIT(6),
@@ -325,7 +301,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main = {
325301
.post_div_table = post_div_table_gpll6_out_main,
326302
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
327303
.width = 4,
328-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
304+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
329305
.clkr.hw.init = &(struct clk_init_data){
330306
.name = "gpll6_out_main",
331307
.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
@@ -338,7 +314,7 @@ static struct clk_alpha_pll gpll7 = {
338314
.offset = 0x7000,
339315
.vco_table = default_vco,
340316
.num_vco = ARRAY_SIZE(default_vco),
341-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
317+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
342318
.clkr = {
343319
.enable_reg = 0x79000,
344320
.enable_mask = BIT(7),
@@ -364,7 +340,7 @@ static struct clk_alpha_pll_postdiv gpll7_out_main = {
364340
.post_div_table = post_div_table_gpll7_out_main,
365341
.num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
366342
.width = 4,
367-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
343+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
368344
.clkr.hw.init = &(struct clk_init_data){
369345
.name = "gpll7_out_main",
370346
.parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
@@ -392,7 +368,7 @@ static struct clk_alpha_pll gpll8 = {
392368
.offset = 0x8000,
393369
.vco_table = default_vco,
394370
.num_vco = ARRAY_SIZE(default_vco),
395-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
371+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
396372
.flags = SUPPORTS_DYNAMIC_UPDATE,
397373
.clkr = {
398374
.enable_reg = 0x79000,
@@ -419,7 +395,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main = {
419395
.post_div_table = post_div_table_gpll8_out_main,
420396
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
421397
.width = 4,
422-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT],
398+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
423399
.clkr.hw.init = &(struct clk_init_data){
424400
.name = "gpll8_out_main",
425401
.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
@@ -443,7 +419,7 @@ static struct clk_alpha_pll gpll9 = {
443419
.offset = 0x9000,
444420
.vco_table = gpll9_vco,
445421
.num_vco = ARRAY_SIZE(gpll9_vco),
446-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
422+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
447423
.clkr = {
448424
.enable_reg = 0x79000,
449425
.enable_mask = BIT(9),
@@ -469,7 +445,7 @@ static struct clk_alpha_pll_postdiv gpll9_out_main = {
469445
.post_div_table = post_div_table_gpll9_out_main,
470446
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
471447
.width = 2,
472-
.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO],
448+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
473449
.clkr.hw.init = &(struct clk_init_data){
474450
.name = "gpll9_out_main",
475451
.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },

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