@@ -39,16 +39,10 @@ struct stm32_exti_bank {
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#define UNDEF_REG ~0
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- struct stm32_desc_irq {
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- u32 exti ;
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- u32 irq_parent ;
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- };
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-
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struct stm32_exti_drv_data {
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const struct stm32_exti_bank * * exti_banks ;
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- const struct stm32_desc_irq * desc_irqs ;
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+ const u8 * desc_irqs ;
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u32 bank_nr ;
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- u32 irq_nr ;
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};
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struct stm32_exti_chip_data {
@@ -176,126 +170,114 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
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static struct irq_chip stm32_exti_h_chip ;
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static struct irq_chip stm32_exti_h_chip_direct ;
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- static const struct stm32_desc_irq stm32mp1_desc_irq [] = {
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- { .exti = 0 , .irq_parent = 6 },
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- { .exti = 1 , .irq_parent = 7 },
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- { .exti = 2 , .irq_parent = 8 },
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- { .exti = 3 , .irq_parent = 9 },
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- { .exti = 4 , .irq_parent = 10 },
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- { .exti = 5 , .irq_parent = 23 },
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- { .exti = 6 , .irq_parent = 64 },
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- { .exti = 7 , .irq_parent = 65 },
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- { .exti = 8 , .irq_parent = 66 },
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- { .exti = 9 , .irq_parent = 67 },
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- { .exti = 10 , .irq_parent = 40 },
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- { .exti = 11 , .irq_parent = 42 },
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- { .exti = 12 , .irq_parent = 76 },
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- { .exti = 13 , .irq_parent = 77 },
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- { .exti = 14 , .irq_parent = 121 },
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- { .exti = 15 , .irq_parent = 127 },
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- { .exti = 16 , .irq_parent = 1 },
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- { .exti = 19 , .irq_parent = 3 },
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- { .exti = 21 , .irq_parent = 31 },
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- { .exti = 22 , .irq_parent = 33 },
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- { .exti = 23 , .irq_parent = 72 },
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- { .exti = 24 , .irq_parent = 95 },
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- { .exti = 25 , .irq_parent = 107 },
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- { .exti = 26 , .irq_parent = 37 },
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- { .exti = 27 , .irq_parent = 38 },
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- { .exti = 28 , .irq_parent = 39 },
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- { .exti = 29 , .irq_parent = 71 },
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- { .exti = 30 , .irq_parent = 52 },
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- { .exti = 31 , .irq_parent = 53 },
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- { .exti = 32 , .irq_parent = 82 },
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- { .exti = 33 , .irq_parent = 83 },
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- { .exti = 47 , .irq_parent = 93 },
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- { .exti = 48 , .irq_parent = 138 },
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- { .exti = 50 , .irq_parent = 139 },
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- { .exti = 52 , .irq_parent = 140 },
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- { .exti = 53 , .irq_parent = 141 },
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- { .exti = 54 , .irq_parent = 135 },
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- { .exti = 61 , .irq_parent = 100 },
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- { .exti = 65 , .irq_parent = 144 },
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- { .exti = 68 , .irq_parent = 143 },
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- { .exti = 70 , .irq_parent = 62 },
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- { .exti = 73 , .irq_parent = 129 },
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+ #define EXTI_INVALID_IRQ U8_MAX
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+ #define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
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+
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+ static const u8 stm32mp1_desc_irq [] = {
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+ /* default value */
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+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1 )] = EXTI_INVALID_IRQ ,
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+
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+ [0 ] = 6 ,
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+ [1 ] = 7 ,
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+ [2 ] = 8 ,
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+ [3 ] = 9 ,
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+ [4 ] = 10 ,
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+ [5 ] = 23 ,
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+ [6 ] = 64 ,
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+ [7 ] = 65 ,
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+ [8 ] = 66 ,
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+ [9 ] = 67 ,
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+ [10 ] = 40 ,
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+ [11 ] = 42 ,
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+ [12 ] = 76 ,
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+ [13 ] = 77 ,
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+ [14 ] = 121 ,
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+ [15 ] = 127 ,
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+ [16 ] = 1 ,
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+ [19 ] = 3 ,
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+ [21 ] = 31 ,
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+ [22 ] = 33 ,
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+ [23 ] = 72 ,
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+ [24 ] = 95 ,
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+ [25 ] = 107 ,
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+ [26 ] = 37 ,
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+ [27 ] = 38 ,
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+ [28 ] = 39 ,
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+ [29 ] = 71 ,
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+ [30 ] = 52 ,
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+ [31 ] = 53 ,
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+ [32 ] = 82 ,
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+ [33 ] = 83 ,
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+ [47 ] = 93 ,
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+ [48 ] = 138 ,
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+ [50 ] = 139 ,
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+ [52 ] = 140 ,
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+ [53 ] = 141 ,
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+ [54 ] = 135 ,
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+ [61 ] = 100 ,
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+ [65 ] = 144 ,
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+ [68 ] = 143 ,
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+ [70 ] = 62 ,
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+ [73 ] = 129 ,
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};
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- static const struct stm32_desc_irq stm32mp13_desc_irq [] = {
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- { .exti = 0 , .irq_parent = 6 },
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- { .exti = 1 , .irq_parent = 7 },
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- { .exti = 2 , .irq_parent = 8 },
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- { .exti = 3 , .irq_parent = 9 },
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- { .exti = 4 , .irq_parent = 10 },
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- { .exti = 5 , .irq_parent = 24 },
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- { .exti = 6 , .irq_parent = 65 },
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- { .exti = 7 , .irq_parent = 66 },
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- { .exti = 8 , .irq_parent = 67 },
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- { .exti = 9 , .irq_parent = 68 },
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- { .exti = 10 , .irq_parent = 41 },
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- { .exti = 11 , .irq_parent = 43 },
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- { .exti = 12 , .irq_parent = 77 },
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- { .exti = 13 , .irq_parent = 78 },
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- { .exti = 14 , .irq_parent = 106 },
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- { .exti = 15 , .irq_parent = 109 },
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- { .exti = 16 , .irq_parent = 1 },
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- { .exti = 19 , .irq_parent = 3 },
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- { .exti = 21 , .irq_parent = 32 },
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- { .exti = 22 , .irq_parent = 34 },
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- { .exti = 23 , .irq_parent = 73 },
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- { .exti = 24 , .irq_parent = 93 },
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- { .exti = 25 , .irq_parent = 114 },
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- { .exti = 26 , .irq_parent = 38 },
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- { .exti = 27 , .irq_parent = 39 },
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- { .exti = 28 , .irq_parent = 40 },
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- { .exti = 29 , .irq_parent = 72 },
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- { .exti = 30 , .irq_parent = 53 },
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- { .exti = 31 , .irq_parent = 54 },
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- { .exti = 32 , .irq_parent = 83 },
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- { .exti = 33 , .irq_parent = 84 },
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- { .exti = 44 , .irq_parent = 96 },
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- { .exti = 47 , .irq_parent = 92 },
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- { .exti = 48 , .irq_parent = 116 },
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- { .exti = 50 , .irq_parent = 117 },
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- { .exti = 52 , .irq_parent = 118 },
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- { .exti = 53 , .irq_parent = 119 },
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- { .exti = 68 , .irq_parent = 63 },
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- { .exti = 70 , .irq_parent = 98 },
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+ static const u8 stm32mp13_desc_irq [] = {
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+ /* default value */
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+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1 )] = EXTI_INVALID_IRQ ,
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+
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+ [0 ] = 6 ,
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+ [1 ] = 7 ,
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+ [2 ] = 8 ,
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+ [3 ] = 9 ,
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+ [4 ] = 10 ,
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+ [5 ] = 24 ,
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+ [6 ] = 65 ,
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+ [7 ] = 66 ,
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+ [8 ] = 67 ,
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+ [9 ] = 68 ,
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+ [10 ] = 41 ,
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+ [11 ] = 43 ,
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+ [12 ] = 77 ,
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+ [13 ] = 78 ,
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+ [14 ] = 106 ,
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+ [15 ] = 109 ,
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+ [16 ] = 1 ,
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+ [19 ] = 3 ,
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+ [21 ] = 32 ,
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+ [22 ] = 34 ,
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+ [23 ] = 73 ,
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+ [24 ] = 93 ,
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+ [25 ] = 114 ,
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+ [26 ] = 38 ,
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+ [27 ] = 39 ,
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+ [28 ] = 40 ,
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+ [29 ] = 72 ,
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+ [30 ] = 53 ,
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+ [31 ] = 54 ,
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+ [32 ] = 83 ,
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+ [33 ] = 84 ,
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+ [44 ] = 96 ,
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+ [47 ] = 92 ,
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+ [48 ] = 116 ,
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+ [50 ] = 117 ,
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+ [52 ] = 118 ,
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+ [53 ] = 119 ,
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+ [68 ] = 63 ,
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+ [70 ] = 98 ,
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};
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static const struct stm32_exti_drv_data stm32mp1_drv_data = {
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.exti_banks = stm32mp1_exti_banks ,
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.bank_nr = ARRAY_SIZE (stm32mp1_exti_banks ),
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.desc_irqs = stm32mp1_desc_irq ,
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- .irq_nr = ARRAY_SIZE (stm32mp1_desc_irq ),
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};
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static const struct stm32_exti_drv_data stm32mp13_drv_data = {
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.exti_banks = stm32mp1_exti_banks ,
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.bank_nr = ARRAY_SIZE (stm32mp1_exti_banks ),
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.desc_irqs = stm32mp13_desc_irq ,
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- .irq_nr = ARRAY_SIZE (stm32mp13_desc_irq ),
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};
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- static const struct
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- stm32_desc_irq * stm32_exti_get_desc (const struct stm32_exti_drv_data * drv_data ,
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- irq_hw_number_t hwirq )
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- {
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- const struct stm32_desc_irq * desc = NULL ;
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- int i ;
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-
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- if (!drv_data -> desc_irqs )
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- return NULL ;
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-
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- for (i = 0 ; i < drv_data -> irq_nr ; i ++ ) {
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- desc = & drv_data -> desc_irqs [i ];
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- if (desc -> exti == hwirq )
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- break ;
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- }
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-
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- return desc ;
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- }
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-
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static unsigned long stm32_exti_pending (struct irq_chip_generic * gc )
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{
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struct stm32_exti_chip_data * chip_data = gc -> private ;
@@ -713,7 +695,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
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{
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struct stm32_exti_host_data * host_data = dm -> host_data ;
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struct stm32_exti_chip_data * chip_data ;
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- const struct stm32_desc_irq * desc ;
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+ u8 desc_irq ;
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struct irq_fwspec * fwspec = data ;
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struct irq_fwspec p_fwspec ;
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irq_hw_number_t hwirq ;
@@ -728,21 +710,21 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
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bank = hwirq / IRQS_PER_BANK ;
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chip_data = & host_data -> chips_data [bank ];
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-
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- desc = stm32_exti_get_desc (host_data -> drv_data , hwirq );
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- if (!desc )
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- return - EINVAL ;
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-
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event_trg = readl_relaxed (host_data -> base + chip_data -> reg_bank -> trg_ofst );
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chip = (event_trg & BIT (hwirq % IRQS_PER_BANK )) ?
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& stm32_exti_h_chip : & stm32_exti_h_chip_direct ;
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irq_domain_set_hwirq_and_chip (dm , virq , hwirq , chip , chip_data );
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- if (desc -> irq_parent ) {
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+
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+ if (!host_data -> drv_data || !host_data -> drv_data -> desc_irqs )
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+ return - EINVAL ;
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+
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+ desc_irq = host_data -> drv_data -> desc_irqs [hwirq ];
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+ if (desc_irq != EXTI_INVALID_IRQ ) {
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p_fwspec .fwnode = dm -> parent -> fwnode ;
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p_fwspec .param_count = 3 ;
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p_fwspec .param [0 ] = GIC_SPI ;
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- p_fwspec .param [1 ] = desc -> irq_parent ;
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+ p_fwspec .param [1 ] = desc_irq ;
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p_fwspec .param [2 ] = IRQ_TYPE_LEVEL_HIGH ;
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return irq_domain_alloc_irqs_parent (dm , virq , 1 , & p_fwspec );
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