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VDavid003krzk
VDavid003
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krzk
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clk: samsung: exynos7885: Implement CMU_FSYS domain
CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks for all MMC devices on Exynos7885, and USB30DRD. Add clocks: - Bus clocks in CMU_TOP needed for CMU_FSYS - All clocks in CMU_FSYS needed for MMC devices Signed-off-by: David Virag <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/clk/samsung/clk-exynos7885.c

Lines changed: 158 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,11 @@
2727
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
2828
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
2929
#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
30+
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028
31+
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c
32+
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030
33+
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034
34+
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038
3035
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
3136
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
3237
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
@@ -39,6 +44,11 @@
3944
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
4045
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
4146
#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
47+
#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844
48+
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848
49+
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c
50+
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850
51+
#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854
4252
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
4353
#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
4454
#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
@@ -59,6 +69,11 @@
5969
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
6070
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
6171
#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
72+
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044
73+
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048
74+
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c
75+
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050
76+
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054
6277
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
6378
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
6479
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
@@ -76,6 +91,11 @@ static const unsigned long top_clk_regs[] __initconst = {
7691
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
7792
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
7893
CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
94+
CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,
95+
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,
96+
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,
97+
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO,
98+
CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD,
7999
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
80100
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
81101
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
@@ -88,6 +108,11 @@ static const unsigned long top_clk_regs[] __initconst = {
88108
CLK_CON_DIV_CLKCMU_CORE_BUS,
89109
CLK_CON_DIV_CLKCMU_CORE_CCI,
90110
CLK_CON_DIV_CLKCMU_CORE_G3D,
111+
CLK_CON_DIV_CLKCMU_FSYS_BUS,
112+
CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,
113+
CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,
114+
CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO,
115+
CLK_CON_DIV_CLKCMU_FSYS_USB30DRD,
91116
CLK_CON_DIV_CLKCMU_PERI_BUS,
92117
CLK_CON_DIV_CLKCMU_PERI_SPI0,
93118
CLK_CON_DIV_CLKCMU_PERI_SPI1,
@@ -108,6 +133,11 @@ static const unsigned long top_clk_regs[] __initconst = {
108133
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
109134
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
110135
CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
136+
CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,
137+
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,
138+
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,
139+
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO,
140+
CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD,
111141
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
112142
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
113143
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
@@ -146,6 +176,13 @@ PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
146176
PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
147177
PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
148178

179+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
180+
PNAME(mout_fsys_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
181+
PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2", "dout_shared1_div2" };
182+
PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2", "dout_shared1_div2" };
183+
PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" };
184+
PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" };
185+
149186
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
150187
/* CORE */
151188
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
@@ -174,6 +211,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
174211
CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
175212
MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
176213
CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
214+
215+
/* FSYS */
216+
MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,
217+
CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
218+
MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p,
219+
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),
220+
MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p,
221+
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),
222+
MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p,
223+
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),
224+
MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p,
225+
CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),
177226
};
178227

179228
static const struct samsung_div_clock top_div_clks[] __initconst = {
@@ -220,6 +269,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
220269
CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
221270
DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
222271
CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
272+
273+
/* FSYS */
274+
DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus",
275+
CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
276+
DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card",
277+
CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
278+
DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd",
279+
CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
280+
DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio",
281+
CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),
282+
DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd",
283+
CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),
223284
};
224285

225286
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
@@ -250,6 +311,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
250311
CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
251312
GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
252313
CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
314+
315+
/* FSYS */
316+
GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus",
317+
CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
318+
GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card",
319+
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
320+
GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd",
321+
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
322+
GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio",
323+
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),
324+
GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd",
325+
CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),
253326
};
254327

255328
static const struct samsung_cmu_info top_cmu_info __initconst = {
@@ -560,6 +633,88 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
560633
.clk_name = "dout_core_bus",
561634
};
562635

636+
/* ---- CMU_FSYS ------------------------------------------------------------ */
637+
638+
/* Register Offset definitions for CMU_FSYS (0x13400000) */
639+
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
640+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
641+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
642+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
643+
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
644+
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
645+
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
646+
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
647+
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
648+
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
649+
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
650+
651+
static const unsigned long fsys_clk_regs[] __initconst = {
652+
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
653+
PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
654+
PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
655+
PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
656+
PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
657+
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
658+
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
659+
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
660+
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
661+
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
662+
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
663+
};
664+
665+
/* List of parent clocks for Muxes in CMU_FSYS */
666+
PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" };
667+
PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
668+
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
669+
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
670+
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
671+
672+
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
673+
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
674+
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),
675+
MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user",
676+
mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
677+
4, 1, CLK_SET_RATE_PARENT, 0),
678+
MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user",
679+
mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
680+
4, 1, CLK_SET_RATE_PARENT, 0),
681+
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
682+
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
683+
4, 1, CLK_SET_RATE_PARENT, 0),
684+
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
685+
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
686+
4, 1, CLK_SET_RATE_PARENT, 0),
687+
};
688+
689+
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
690+
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
691+
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
692+
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
693+
"mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
694+
21, CLK_SET_RATE_PARENT, 0),
695+
GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user",
696+
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),
697+
GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
698+
"mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
699+
21, CLK_SET_RATE_PARENT, 0),
700+
GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user",
701+
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),
702+
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
703+
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
704+
21, CLK_SET_RATE_PARENT, 0),
705+
};
706+
707+
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
708+
.mux_clks = fsys_mux_clks,
709+
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
710+
.gate_clks = fsys_gate_clks,
711+
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
712+
.nr_clk_ids = FSYS_NR_CLK,
713+
.clk_regs = fsys_clk_regs,
714+
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
715+
.clk_name = "dout_fsys_bus",
716+
};
717+
563718
/* ---- platform_driver ----------------------------------------------------- */
564719

565720
static int __init exynos7885_cmu_probe(struct platform_device *pdev)
@@ -577,6 +732,9 @@ static const struct of_device_id exynos7885_cmu_of_match[] = {
577732
{
578733
.compatible = "samsung,exynos7885-cmu-core",
579734
.data = &core_cmu_info,
735+
}, {
736+
.compatible = "samsung,exynos7885-cmu-fsys",
737+
.data = &fsys_cmu_info,
580738
}, {
581739
},
582740
};

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