Merge pull request #205 from maleadt/vc/fneg

Add `fneg` opcode for LLVM10

Author: maleadt

src/core/instructions.jl

@@ -99,7 +99,7 @@ Base.delete!(md::InstructionMetadataDict, kind::MD) =
 ## instruction types
 
 const opcodes = [:Ret, :Br, :Switch, :IndirectBr, :Invoke, :Unreachable, :Add, :FAdd, :Sub,
-                 :FSub, :Mul, :FMul, :UDiv, :SDiv, :FDiv, :URem, :SRem, :FRem, :Shl, :LShr,
+                 :FSub, :FNeg, :Mul, :FMul, :UDiv, :SDiv, :FDiv, :URem, :SRem, :FRem, :Shl, :LShr,
                  :AShr, :And, :Or, :Xor, :Alloca, :Load, :Store, :GetElementPtr, :Trunc,
                  :ZExt, :SExt, :FPToUI, :FPToSI, :UIToFP, :SIToFP, :FPTrunc, :FPExt,
                  :PtrToInt, :IntToPtr, :BitCast, :AddrSpaceCast, :ICmp, :FCmp, :PHI, :Call,

test/irbuilder.jl

@@ -261,7 +261,11 @@ LLVM.Module("SomeModule", ctx) do mod
     @check_ir nuwneginst "sub nuw i32 0, %0"
 
     fneginst = fneg!(builder, float1)
-    @check_ir fneginst "fsub float -0.000000e+00, %2"
+    if LLVM.version() < v"10.0.0"
+        @check_ir fneginst "fsub float -0.000000e+00, %2"
+    else
+        @check_ir fneginst "fneg float %2"
+    end
 
     notinst = not!(builder, int1)
     @check_ir notinst "xor i32 %0, -1"